PC87382 datasheet(16/72 Pages) NSC

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2.0 Power, Reset and Clocks (Continued)

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Revision1.2

Bit 4 (read only) of the CLOCKCF register is the Valid Clock Generator status bit. While stabilizing, the output clock is frozen

to a steady logic level, and the status bit is cleared to 0 to indicate a frozen clock. When the clock generator is stable, the output

clock starts toggling and the status bit is set to 1. The status bit tells the software when the Clock Generator is ready. The soft-

ware should poll this status bit until it is set (1), and only then activate the UART, the Infrared interface and the DCLKOUT pin.

The clock generator and its output clock do not consume power when they are disabled.

2.3.3

Chip Power-Up

To ensure proper operation, proceed as follows after power-up:

1. Set bits 5 and 6 of the Clock Generator Control register (CLOCKCF) at Index 29h according to the clock source used

and the desired output frequency on DCLKOUT; see Table 4.

2. Enable the clock. If the clock source is 14.31818 MHz:

— Poll bit 4 of the CLOCKCF register while the clock generator is stabilizing.

— When bit 4 of CLOCKCF is set to 1, go to step 3.

3. Enable any module in the chip, as needed.

Table 4. Clock Generator Encoding Options

2.3.4

Specifications

Wake-up time is 33 msec (maximum). This is measured from the time the Clock Generator is enabled until the clock is stable.

Note: The reference clock must be stable at the time the Clock Generator is enabled. Tolerance (long term deviation) of

the generator output clock, relative to the input clock, is

±110 ppm. Total tolerance is therefore

± (input clock tolerance + 110 ppm).

2.4

TESTABILITY SUPPORT

The PC87382 supports two testability modes:

• In-Circuit Testing (ICT)

• XOR Tree Testing

2.4.1

ICT

The In-Circuit Testing (ICT) technique, also known as “bed-of-nails”, injects logic patterns to the input pins of the devices

mounted on the tested board. It then checks their outputs for the correct logic levels.

The PC87382 supports this testing technique by floating (putting in TRI-STATE) all the device pins. This prevents “back-

driving” the PC87382 pins by the ICT tester when a device normally controlled by PC87382 is tested (device inputs are driv-

en by the ICT tester).

2.4.2

XOR Tree Testing

When the PC87382 is mounted on a board, it can be tested using the XOR Tree technique. This test also checks the correct

connection of the device pins to the board.

In XOR Tree mode, all PC87382 pins are configured as inputs, except the last pin in the tree, which is the XOR_OUT output. The

buffer type of the input pins participating in the XOR tree is INT (Input, TTL compatible), regardless of the buffer type of these pins

in normal device operation mode (see Section 1.3 on page 10). The input pins are chained through XOR gates, as shown in

Figure 2. The power and ground pins (VDD, VSS, VCORF) are excluded from the XOR tree.

CLKIN Pin Frequency

Desired DCLKOUT Frequency

CLOCKCF Bits 6, 5

48 MHz

14.31818 MHz

48 MHz

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