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PC87382 датащи(PDF) 47 Page - National Semiconductor (TI) |
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PC87382 датащи(HTML) 47 Page - National Semiconductor (TI) |
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47 / 72 page ![]() 7.0 Legacy Functional Blocks (Continued) Revision 1.2 47 www.national.com 7.1 SERIAL PORT 1 (SP1) 7.1.1 General Description The Serial Port functional block supports serial data communication with a remote peripheral device or modem using a wired interface. The Serial Port can function in one of three modes: q 16450-Compatible mode (Standard 16450) q 16550-Compatible mode (Standard 16550) q Extended mode Extended mode provides advanced functionality for the UART. The Serial Port provides receive and transmit channels that can operate concurrently in full-duplex mode. It performs all functions required to conduct parallel data interchange with the system and composite serial data exchange with the external data channel, including: q Format conversion between the internal parallel data format and the external programmable composite serial format q Serial data timing generation and recognition q Parallel data interchange with the system using a choice of bidirectional data transfer mechanisms q Status monitoring for all phases of communication activity q Complete MODEM-control capability. Existing 16550-based legacy software is completely and transparently supported. Module organization and specific fallback mechanisms switch the module to 16550-Compatible mode on reset or when initialized by 16550 software. 7.1.2 Register Bank Overview Four register banks, each containing eight registers, control Serial Port operation. All registers use the same 8-byte address space to indicate offsets 00h through 07h. The active bank must be selected by the software. The register bank organization enables access to the banks as required for activation of all module modes, while maintaining transparent compatibility with 16450 or 16550 software. The Bank Selection register (BSR) selects the active bank and is common to all banks as shown in Figure 12. Therefore, each bank defines seven new registers. The default bank selection after system reset is 0. Figure 12. Register Bank Architecture BANK 0 BANK 1 BANK 2 BANK 3 Offset 07h Offset 06h Offset 05h Offset 04h LCR/BSR Offset 02h Offset 01h Offset 00h Common Register Throughout All Banks 16550 Banks |
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