PC87382 datasheet(6/72 Pages) NSC

6 / 72 page

Table of Contents (Continued)

www.national.com

Revision 1.2

5.3

EVENT HANDLING AND SYSTEM NOTIFICATION ................................................................ 40

5.3.1

Event Configuration ..................................................................................................... 40

5.3.2

System Notification ...................................................................................................... 40

5.4

GPIO PORT REGISTERS ......................................................................................................... 41

5.4.1

GPIO Pin Configuration Registers Structure ............................................................... 42

5.4.2

GPIO Port Runtime Register Map ............................................................................... 42

5.4.3

GPIO Data Out Register (GPDO) ................................................................................ 42

5.4.4

GPIO Data In Register (GPDI) .................................................................................... 43

5.4.5

GPIO Event Enable Register (GPEVEN) .................................................................... 43

5.4.6

GPIO Event Status Register (GPEVST) ...................................................................... 43

6.0

Docking LPC Switch

6.1

OVERVIEW ............................................................................................................................... 44

6.2

FUNCTIONAL DESCRIPTION .................................................................................................. 44

6.2.1

Basic Functionality ....................................................................................................... 44

6.2.2

LDRQ Sharing Mechanism .......................................................................................... 44

6.3

DOCKING LPC SWITCH REGISTERS ..................................................................................... 45

6.3.1

Docking LPC Switch Register Map .............................................................................. 45

6.3.2

Docking LPC Control (DLCTL) .................................................................................... 45

7.0

Legacy Functional Blocks

7.1

SERIAL PORT 1 (SP1) .............................................................................................................. 47

7.1.1

General Description ..................................................................................................... 47

7.1.2

7.1.3

SP1 Register Maps ...................................................................................................... 48

7.1.4

SP1 Bitmap Summary ................................................................................................. 49

7.2

IR FUNCTIONALITY (IR) ........................................................................................................... 51

7.2.1

General Description ..................................................................................................... 51

7.2.2

7.2.3

IR Register Map for IR Functionality ............................................................................ 52

7.2.4

IR Bitmap Summary for IR Functionality

................................................................. 55

8.0

Device Characteristics

8.1

GENERAL DC ELECTRICAL CHARACTERISTICS ................................................................. 58

8.1.1

Recommended Operating Conditions ......................................................................... 58

8.1.2

Absolute Maximum Ratings ......................................................................................... 58

8.1.3

Capacitance ................................................................................................................59

8.1.4

Power Consumption under Recommended Operating Conditions .............................. 59

8.1.5

Voltage Thresholds ...................................................................................................... 59

8.2

DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES .................................................. 59

8.2.1

Input, PCI 3.3V ............................................................................................................59

8.2.2

Input, TTL Compatible ................................................................................................. 60

8.2.3

Input, TTL Compatible with Schmitt Trigger ................................................................ 60

8.2.4

Output, PCI 3.3V ......................................................................................................... 60

PC87382 датащи(PDF) 6 Page - National Semiconductor (TI)

PC87382 датащи(HTML) 6 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

датащи скачать

ссылки URL