DS3134 datasheet(114/203 Pages) DALLAS

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DS3134

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Status Bits / Interrupts

On writes to the Done Queue by the DMA, the DMA will set the Status Bit for Receive DMA Done

Queue Write (RDQW) in the Status Register for DMA (SDMA). The Host can configure the DMA to

either set this status bit on each write to the Done Queue or only after multiple (from 2 to 128) writes.

The Host controls this by setting the RDQT0 to RDQT2 bits in the Receive DMA Queues Control

(RDMAQ) register. See the description of the RDMAQ register at the end of Section 8.1.4 for more

details. The DMA also checks the Receive Done Queue Host Read Pointer to make sure that an overflow

does not occur. If this does occur, then the DMA will set the Status Bit for Receive DMA Done Queue

Write Error (RDQWE) in the Status Register for DMA (SDMA) and it will not write to the Done Queue

nor will it increment the Write Pointer. In such a scenario, packets may be lost and unrecoverable. Each

of the status bits can also (if enabled) cause a hardware interrupt to occur. See Section 4 for more details.

Buffer Write Threshold Setting

In the DMA Configuration RAM (see Section 8.1.5), there is a Host controlled field called Threshold

(bits RDT0 to RDT2) that informs the DMA on when it should write to the Done Queue. The Host has

the option to have the DMA place information in the Done Queue after a programmable number (from 1

to 7) data buffers have been filled or wait until the completed packet data has been written. The DMA

will always write to the Done Queue when it has finished receiving a packet even if the threshold has not

been met.

Done Queue Burst Writing

The DMA has the ability to write to the Done Queue in bursts. This allows for a more efficient use of the

PCI Bus. The DMA can hand off descriptors to the Done Queue in-groups rather than one at a time,

freeing up the PCI Bus for more time critical functions.

Internal to the device there is a FIFO that can store up to 8 Done Queue Descriptors (8 dwords since each

descriptor occupies one dword). The Host must configure the FIFO for proper operation via the Receive

DMA Queues Control (RDMAQ) register (see below).

When enabled via the Receive Done Queue FIFO Enable (RDQFE) bit, the Done Queue FIFO will not

write to the Done Queue until it reaches the High Water Mark. When the Done Queue FIFO reaches the

High Water Mark (which is six descriptors), it will attempt to empty the Done Queue FIFO by burst

writing to the Done Queue. Before it writes to the Done Queue, it checks (by examining the Receive

Done Queue Host Read Pointer) to make sure that the Done Queue has enough room to empty the Done

Queue FIFO. If the Done Queue does not have enough room, then it will only burst write enough

descriptors to keep from overflowing the Done Queue. If the FIFO detects that there is no room for any

descriptors to be written, then it will set the Status Bit for Receive DMA Done Queue Write Error

(RDQWE) in the Status Register for DMA (SDMA) and it will not write to the Done Queue nor will it

increment the Write Pointer. In such a scenario, packets may be lost and unrecoverable. If the Done

Queue FIFO can write descriptors to the Done Queue, then it will burst write them, increment the write

pointer, and set the Status Bit for Receive DMA Done Queue Write (RDQW) in the Status Register for

DMA (SDMA). See Section 4 for more details on Status bits.

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