DS3134 datasheet(109/203 Pages) DALLAS

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DS3134

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Status / Interrupts

On each read of the Free Queue by the DMA, the DMA will set either the Status Bit for Receive DMA

Large Buffer Read (RLBR) or the Status Bit for Receive DMA Small Buffer Read (RSBR) in the Status

Pointer and the Receive Free Queue Small Buffer Host Write Pointer to make sure that an underflow does

not occur. If it does occur, then the DMA will set either the Status Bit for Receive DMA Large Buffer

Read Error (RLBRE) or the Status Bit for Receive DMA Small Buffer Read Error (RSBRE) in the Status

such a scenario, the Receive FIFO may overflow if the Host does not provide Free Queue Descriptors.

Each of the status bits can also (if enabled) cause a hardware interrupt to occur. See Section 4 for more

details.

Free Queue Burst Reading

The DMA has the ability to read the Free Queue in bursts. This allows for a more efficient use of the PCI

Bus. The DMA can grab messages from the Free Queue in a group rather than one at a time, freeing up

the PCI Bus for more time critical functions.

Internal to the device there is a FIFO that can store up to 16 Free Queue Descriptors (32 dwords since

each descriptor occupies two dwords). The Free Queue can either operate in dual or singular circular

queue mode. The Free Queue can be divided into Large Buffer and Small Buffer. The LBSA (Large

Buffer Starting Address) and the LBEA (Large Buffer Ending Address) forms the Large Buffer Queue

and the SBSA (Small Buffer Starting Address) and the RFQEA (Receive Free Queue End Address) forms

the Small Buffer Queue. When the SBSA is not equal to, and greater than, the RFQEA the Free Queue is

set up in a dual circular mode. If the SBSA is equal to the RFQEA, the Free Queue is operating in a single

queue mode. When the Free Queue is operated as a dual circular queue supporting both large and small

buffers, then the FIFO is cut into two 8 message FIFOs. If the Free Queue is operated as a single circular

queue supporting only the large buffers, then the FIFO is set up as a single 16 descriptor FIFO. The Host

must configure the Free Queue FIFO for proper operation via the Receive DMA Queues Control

(RDMAQ) register (see below).

When enabled via the Receive Free Queue FIFO Enable (RFQFE) bit, the Free Queue FIFO will not read

the Free Queue until it reaches the Low Water Mark. When the FIFO reaches the Low Water Mark

(which is two descriptors in the dual mode or four descriptors in the single mode,) it will attempt to fill

the FIFO with additional descriptors by burst reading the Free Queue. Before it reads the Free Queue, it

checks (by examining the Receive Free Queue Host Write Pointer) to make sure that the Free Queue

contains enough descriptors to fill the Free Queue FIFO.

If the Free Queue does not have enough

descriptors to fill the FIFO, then it will only read enough to keep from underflowing the Free Queue. If

the FIFO detects that there are no Free Queue descriptors available for it to read, then it will set the either

the Status Bit for Receive DMA Large Buffer Read Error (RLBRE) or the Status Bit for Receive DMA

Small Buffer Read Error (RSBRE) in the Status Register for DMA (SDMA) and it will not read the Free

Queue nor will it increment the Read Pointer. In such a scenario, the Receive FIFO may overflow if the

Host does not provide Free Queue Descriptors. If the Free Queue FIFO can read descriptors from the

Free Queue, then it will burst read them, increment the read pointer, and set either the Status Bit for

Receive DMA Large Buffer Read (RLBR) or the Status Bit for Receive DMA Small Buffer Read (RSBR)

in the Status Register for DMA (SDMA). See Section 4 for more details on Status Bits.

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