PC87365 datasheet(178/215 Pages) NSC

178 / 215 page

10.0 Temperature Sensor (TMS) (Continued)

178

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10.3.7

Temperature Channel Configuration and Status Register (TCHCFST)

This register is set to 00h on power-up of AVDD. Bits 3-1 indicate which of three temperature limits has been exceeded. Write

1 to clear any of these bits. Writing 0 has no effect.

Location:

Offset 0Ah

Type:

Varies per bit

Bit

76543210

Name

End of

Conversion

Open

OTS Output

Enable

ALERT

Output

Enable

Channel

Overtemp

Limit

Exceeded

Channel

Temp High

Limit

Exceeded

Channel

Temp Low

Limit

Exceeded

Channel

Enable

Reset

00000000

Bit

Type

Description

R/W1C End of Conversion. This bit reﬂects the data in the RDCHT register (see next page). It is cleared by

writing 1 to this bit. It is set when new data is written to the RDCHT register.

0: No new data (default)

1: New data not yet read

R/W1C Open.

0: No fault (default)

1: Remote diode continuity (open circuit) fault

R/W OTS Output Enable.

0: Disabled (default)

1: Enabled

R/W ALERT Output Enable.

0: Disabled (default)

1: Enabled

R/W1C Channel Overtemperature Limit Exceeded.

0: Overtemperature lower than limit (default)

1: Overtemperature higher than limit

R/W1C Channel Temperature High Limit Exceeded.

0: Temperature lower than limit (default)

1: Temperature higher than limit

R/W1C Channel Temperature Low Limit Exceeded. This bit is set whenever a value lower than the value

speciﬁed in CHTL is written into RDCHT. It is cleared by writing 1 to it.

0: Temperature higher than limit (default)

1: Temperature lower than limit

R/W Channel Enable.

0: Disabled (default)

1: Enabled

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