LP8501 datasheet(33/51 Pages) TI1

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LP8501

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SNVS548D – SEPTEMBER 2008 – REVISED AUGUST 2013

Table 5. Control Register Map (continued)

Hex

Bit(s)

Read/Wr

Default Value

Bit Mnemonic and Description

Address

ite

After Reset

D5 CURRENT CONTROL

[7:0]

R/W

10101111

CURRENT

D5 output current control register. Default current is

17.5 mA (typ.)

D6 CURRENT CONTROL

[7:0]

R/W

10101111

CURRENT

D6 output current control register. Default current is

17.5 mA (typ.)

D7 CURRENT CONTROL

[7:0]

R/W

10101111

CURRENT

D7 output current control register. Default current is

17.5 mA (typ.)

D8 CURRENT CONTROL

[7:0]

R/W

10101111

CURRENT

D8 output current control register. Default current is

17.5 mA (typ.)

D9 CURRENT CONTROL

[7:0]

R/W

10101111

CURRENT

D9 output current control register. Default current is

17.5 mA (typ.)

2F TO 35

RESERVED FOR FUTURE

[7:0]

RESERVED FOR FUTURE USE

USE

CONFIG

[7]

R/W

0xxxxx0x

PWM_POWERSAVE

Enables PWM powersave option

[6]

R/W

x1xxxx0x

EN_AUTO_INCR

Serial bus address auto increment enable

[5]

R/W

xx0xxx0x

POWERSAVE_EN

Powersave mode enable

[4:3]

R/W

xxx00x0x

CP_MODE

Charge pump gain selection

[2]

R/W

xxxxx00x

FADE_TO_OFF

Automatic fade out enable

[1]

R/W

xxxxxx0x

RESERVED Note that this bit should always be set

to zero when writing register.

[0]

R/W

xxxxxx00

INT_CLK_EN

LED Clock source selection

ENGINE1 PC

[6:0]

R/W

x0000000

Program counter for engine 1

ENGINE2 PC

[6:0]

R/W

x0000000

Program counter for engine 2

ENGINE3 PC

[6:0]

R/W

x0000000

Program counter for engine 3

STATUS/INTERRUPT

[7]

0xxxxxxx

LED_TEST_MEASUREMENT_DONE

Indicates when the LED test measurement is done.

[6]

x1xxxxxx

MASK_BUSY

Mask bit for interrupt generated by START_UP

BUSY or ENGINE_BUSY

[5]

xx0xxxxx

START_UP BUSY

This bit indicates that the start-up sequence is

running

[4]

xxx0xxxx

ENGINE_BUSY

This bit indicates that a program execution engine is

clearing internal registers

[3]

xxxx0xxx

EXT_CLK_USED

Indicates when external clock signal bit is set

[2]

xxxxx0xx

ENG1_INT

Interrupt bit for program execution engine 1

[1]

xxxxxx0x

ENG2_INT

Interrupt bit for program execution engine 2

[0]

xxxxxxx0

ENG3_INT

Interrupt bit for program execution engine 3

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