LP8501 datasheet(27/51 Pages) TI1

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Input

Buffer

Level

Shifter

Level

Shifter

SDA

SCL

VDD

LP8501

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SNVS548D – SEPTEMBER 2008 – REVISED AUGUST 2013

IO LEVELS

I2C interface, CLK and TRIG pin input levels are defined by the EN pin. Using the EN pin as voltage reference for

logic inputs simplifies PWR routing and eliminates the need for a dedicated VIO pin. In the following block

diagram EN pin connections are illustrated.

Figure 24. Using EN Pin As Digital IO Voltage Reference

GPO/INT Pins

The LP8501 has one General Purpose Output pin (GPO); the INT pin also can be configured as a GPO pin. The

GPO pin level is defined by VDD voltage. It also has its own PWM control register. GPO can be configured into

fader groups, and it can be used in LED engine programming. When INT is configured as GPO, its level is

defined by the VDD. State of the pins can be controlled with GPO register (3Bh). GPO pins are digital CMOS

outputs, and no pull-up/down resistors are needed.

When the INT pin GPO function is disabled, it operates as an open drain pin. The INT signal is active low, i.e.,

when interrupt signal is sent, the pin is pulled to GND. External pull-up resistor is needed for proper functionality.

Table 4. GPO register (3Bh)

Name

Bit

Description

INT_CONF

Enable INT pin GPO function

0 = INT pin functions as a INT pin

1 = INT pin functions as a GPO pin

GPO

0 = GPO pin state is low

1 = GPO pin state is high

GPO_INT

0 = INT pin state is low (INT_CONF=1)

1 = INT pin state is high (INT_CONF=0)

TRIG Pin

The TRIG pin can function as an external trigger input or output. The external trigger signal is active low if, when

trigger is sent/received, the pin is pulled to GND. TRIG is an open drain pin, and an external pull-up resistor is

needed for trigger line. The external trigger input signal must be at least two 32 kHz clock cycles long to be

recognized. Trigger output signal is three 32 kHz clock cycles long. If TRIG pin is not used on application, it

should be connected to GND to prevent floating of this pin and extra current consumption.

CLK Pin

The CLK pin is used for connecting an external 32 kHz clock to the LP8501. Using an external clock can improve

automatic power-save mode efficiency because the internal clock can be switched off automatically when the

device has entered powersave mode with an external clock present. The device can be used without the external

clock. If an external clock is not used on the application, the CLK pin should be connected to GND to prevent

floating of this pin and extra current consumption.

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