TMS320VC5401 datasheet(28/81 Pages) TI

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Functional Overview

December 2000 − Revised February 2004

SPRS153C

Table 3−5. Bank-Switching Control Register (BSCR) Fields

BIT

RESET

FUNCTION

NO.

NAME

RESET

VALUE

FUNCTION

15−12

BNKCMP

1111

Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of an

address. For example, if BNKCMP = 1111b, the four MSBs (bits 12−15) are compared, resulting in a bank

size of 4K words. Bank sizes of 4K words to 64K words are allowed.

PS - DS

Program read − data read access. Inserts an extra cycle between consecutive accesses of program read

and data read or data read and program read.

PS-DS = 0

No extra cycles are inserted by this feature.

PS-DS = 1

One extra cycle is inserted between consecutive data and program reads.

10−3

Reserved

These bits are reserved and are unaffected by writes.

HBH

HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset

HBH = 0

The bus holder is disabled.

HBH = 1

The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the

previous logic level.

Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset.

BH = 0

The bus holder is disabled.

BH = 1

The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the

previous logic level.

External bus interface off. The EXIO bit controls the external bus-off function.

EXIO = 0

The external bus interface functions as usual

EXIO

EXIO = 0

The external bus interface functions as usual.

EXIO = 1

The address bus, data bus, and control signals become inactive after completing the

t b

l N t th t th DROM MP/MC

d OVLY bit i th PMST

d th HM

current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM

bit of ST1 cannot be modified when the interface is disabled.

3.4

Parallel I/O Ports

The 5401 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW

instruction. The IS signal indicates a read/write operation through an I/O port. The 5401 can interface easily

with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.

3.4.1 Enhanced 8-Bit Host-Port Interface (HPI8)

The 5401 host-port interface, also referred to as the HPI8, is an enhanced version of the standard 8-bit HPI

found on earlier 54x DSPs (542, 545, 548, and 549). The HPI8 is an 8-bit parallel port for interprocessor

communication. The features of the HPI8 include:

Standard features:

•

Sequential transfers (with autoincrement) or random-access transfers

•

Host interrupt and 54x interrupt capability

•

Multiple data strobes and control pins for interface flexibility

Enhanced features of the 5401 HPI8:

•

Access to entire on-chip RAM through DMA bus

•

Capability to continue transferring during emulation stop

The HPI8 functions as a slave and enables the host processor to access the on-chip memory of the 5401.

A major enhancement to the 5401 HPI over previous versions is that it allows host access to the entire on-chip

memory range of the DSP. The HPI8 memory map (see Figure 3−8) is identical to that of the DMA controller

shown in Figure 3−10. The host and the DSP both have access to the on-chip RAM at all times and host

accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same

location, the host has priority, and the DSP waits for one HPI8 cycle. Note that since host accesses are always

synchronized to the 5401 clock, an active input clock (CLKIN) is required for HPI8 accesses during IDLE

states, and host accesses are not allowed while the 5401 reset pin is asserted.

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