TMS320VC5401 datasheet(22/81 Pages) TI

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Functional Overview

December 2000 − Revised February 2004

SPRS153C

3.2

Memory Map

Page 0 Program

Hex

Data

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

MP/MC= 0

(Microcomputer Mode)

MP/MC= 1

(Microprocessor Mode)

0000

0FFF

1000

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

Interrupts

(External)

FF80

Memory Mapped

Registers

On-Chip DARAM

(4K x 16-bit)

ROM (DROM=1)

or External

(DROM=0)

0080

FFFF

Hex

0000

FF7F

FF00

FEFF

EFFF

F000

FFFF

3FFF

4000

0060

007F

0000

Hex

Page 0 Program

External

Scratch-Pad

RAM†

Reserved

(DROM=1)

or External

(DROM=0)

005F

Reserved

(OVLY = 1)

External

(OVLY = 0)

3FFF

4000

FF00

FEFF

EFFF

F000

External

On-Chip ROM

(4K x 16-bit)

Interrupts

(On-Chip)

3FFF

4000

FF7F

FF80

1FFF

2000

1FFF

2000

1FFF

2000

Reserved

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

On-Chip DARAM

(4K x 16-bit)

Reserved

0FFF

1000

2FFF

3000

0FFF

1000

2FFF

3000

2FFF

3000

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

Reserved

(OVLY = 1)

External

(OVLY = 0)

Reserved

(OVLY = 1)

External

(OVLY = 0)

† The scratch-pad RAM area is physically a part of the DARAM block starting at address 1000h. Physical location can

affect multiple access performance. (See Section 3.1.2.)

Figure 3−2. Memory Map

3.2.1 Relocatable Interrupt Vector Table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning

that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes

the code at the vector location. Four words are reserved at each vector location to accommodate a delayed

branch instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the

appropriate interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.

However, these vectors can be remapped to the beginning of any 128-word page in program space after

device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see

Figure 3−3) with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or

trap vector is mapped to the new 128-word page.

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