TMS320VC5401 datasheet(25/81 Pages) TI

25 / 81 page

Functional Overview

December 2000 − Revised February 2004

SPRS153C

0 0000

1 0000

1 3FFF

Page 1

Lower

16K}

External

2 0000

2 3FFF

Page 2

Lower

16K}

External

. . .

F 0000

F 3FFF

Page 15

Lower

16K}

External

0 FFFF

Page 0

64K

Words{

1 4000

1 FFFF

Page 1

Upper

48K

External

2 4000

2 FFFF

Page 2

Upper

48K

External

. . .

F 4000

F FFFF

Page 15

Upper

48K

External

† See Figure 3−2.

‡ The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM and

reserved addresses are mapped to the lower 16K words of all program space pages.

Figure 3−4. Extended Program Memory

3.3

On-Chip Peripherals

The 5401 device has the following peripherals:

•

Software-programmable wait-state generator with programmable bank-switching wait states

•

An enhanced 8-bit host-port interface (HPI8)

•

Two multichannel buffered serial ports (McBSPs)

•

Two hardware timers

•

A clock generator with a phase-locked loop (PLL)

•

A direct memory access (DMA) controller

3.3.1 Software-Programmable Wait-State Generator

The software wait-state generator of the 5401 can extend external bus cycles by up to fourteen machine

cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line.

When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator

are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the

5401.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs

of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five

separate address ranges. This allows a different number of wait states for each of the five address ranges.

Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)

defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is

initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown

in Figure 3−5 and described in Table 3−3.

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