TMS320VC5401 datasheet(36/81 Pages) TI

36 / 81 page

Functional Overview

December 2000 − Revised February 2004

SPRS153C

Table 3−8. DMA Interrupts

MODE

DINM

IMOD

INTERRUPT

ABU (non-decrement)

At full buffer only

ABU (non-decrement)

At half buffer and full buffer

Multi-Frame

At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)

Multi-Frame

At end of frame and end of block (DMCTRn = 0)

Either

No interrupt generated

Either

No interrupt generated

3.8.10

DMA Controller Synchronization Events

The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN

bit field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization

event for a channel. The list of possible events and the DSYN values are shown in Table 3−9.

Table 3−9. DMA Synchronization Events

DSYN VALUE

DMA SYNCHRONIZATION EVENT

0000b

No synchronization used

0001b

McBSP0 receive event

0010b

McBSP0 transmit event

0011−0100b

Reserved

0101b

McBSP1 receive event

0110b

McBSP1 transmit event

0111b−0110b

Reserved

1101b

Timer0 interrupt

1110b

External interrupt 3

1111b

Timer1 interrupt

3.8.11

DMA Channel Interrupt Selection

The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources

for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an

interrupt line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1

shares an interrupt line with timer 1 (IMR/IFR bit 7). The interrupt source for DMA channel 0 is shared with

a reserved interrupt source. When the 5401 is reset, the interrupts from these four DMA channels are

deselected. The INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be

used to select these interrupts, as shown in Table 3−10.

Table 3−10. DMA Channel Interrupt Selection

INTSEL Value

IMR/IFR[6]

IMR/IFR[7]

IMR/IFR[10]

IMR/IFR[11]

00b (reset)

Reserved

TINT1

BRINT1

BXINT1

01b

Reserved

TINT1

DMAC2

DMAC3

10b

DMAC0

DMAC1

DMAC2

DMAC3

11b

Reserved

3.9

Memory-Mapped Registers

The 5401 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h

to 1Fh. Table 3−11 gives a list of CPU memory-mapped registers (MMRs) available on 5401. The device also

has a set of memory-mapped registers associated with peripherals. Table 3−12, Table 3−13, and Table 3−14

show additional peripheral MMRs associated with the 5401.

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