TMS320VC5401 datasheet(21/81 Pages) TI

21 / 81 page

Functional Overview

December 2000 − Revised February 2004

SPRS153C

Table 3−1. Standard On-Chip ROM Layout†

ADDRESS RANGE

DESCRIPTION

F000h − F7FFh

Reserved

F800h − FBFFh

Bootloader

FC00h − FCFFh

µ-law expansion table

FD00h − FDFFh

A-law expansion table

FE00h − FEFFh

Sine look-up table

FF00h − FF7Fh

Reserved

FF80h − FFFFh

Interrupt vector table

† In the 5401 ROM, 128 words are reserved for factory device-testing purposes. Application code to

be implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh in

program space.

3.1.2 On-Chip RAM

The 5401 device contains 8K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of

two blocks of 4K words each. Each DARAM block can support two reads in one cycle, or a read and a write

in one cycle. This allows code to be executed out of one block while two data values are read out of the other

block without incurring a cycle penalty. The first DARAM block occupies two address ranges: 0060h−007Fh

and 1000h−1FFFh in data space. The second DARAM block occupies 2000h−2FFFh in data space. In

program space, each block occupies the same address ranges with the exception of 0060h−007Fh, which

are not available.

3.1.3 On-Chip Memory Security

The 5401 features a 16K-word × 16-bit on-chip maskable ROM.

Customers can arrange to have the ROM of the 5401 programmed with contents unique to any particular

application. A security option is available to protect a custom ROM. The ROM and ROM/RAM security options

are available on the 5401. These security options are described in the TMS320C54x DSP Reference Set,

Volume 1: CPU and Peripherals (literature number SPRU131). When the security options are enabled, JTAG

emulation is inhibited or nonfunctional.

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