TMS320VC5401 datasheet(23/81 Pages) TI

23 / 81 page

Functional Overview

December 2000 − Revised February 2004

SPRS153C

NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR

with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

IPTR

R/W

IPTR

MP/MC

OVLY

AVIS

DROM

CLKOFF

SMUL

SST

R/W

LEGEND: R = Read, W = Write, n = value present after reset

Figure 3−3. Processor Mode Status (PMST) Register

Table 3−2. Processor Mode Status (PMST) Register Bit Fields

BIT

RESET

FUNCTION

NO.

NAME

RESET

VALUE

FUNCTION

15−7

IPTR

1FFh

Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt vectors

reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these bits are

all set to 1; the reset vector always resides at address FF80h in program memory space. The RESET

instruction does not affect this field.

MP/MC

Microprocessor/microcomputermode. MP/MC enables/disables the on-chip ROM to be addressable in

program memory space.

MP/MC = 0: The on-chip ROM is enabled and addressable.

MP/MC = 1: The on-chip ROM is not available.

MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This

pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can also

be set or cleared by software.

OVLY

RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space.

The values for the OVLY bit are:

OVLY = 0: The on-chip RAM is addressable in data space but not in program space.

OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0 (addresses

0h to 7Fh), however, is not mapped into program space.

AVIS

Address visibility mode. AVIS enables/disables the internal program address to be visible at the address

pins.

AVIS = 0: The external address lines do not change with the internal program address. Control and data

lines are not affected and the address bus is driven with the last address on the bus.

AVIS = 1: This mode allows the internal program address to appear at the pins of the 5410A so that

the internal program address can be traced. Also, it allows the interrupt vector to be decoded in

conjunction with IACK when the interrupt vectors reside on on-chip memory.

DROM

Data ROM. DROM enables on-chip ROM to be mapped into data space. The values for the DROM bit

are:

DROM = 0: The on-chip ROM is not mapped into data space.

DROM = 1: A portion of the on-chip RAM is mapped into data space.

CLKOFF

CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high

level.

SMUL

Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before

performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1

and FRCT = 1.

SST

Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before

storing in memory. The saturation is performed after the shift operation.

TMS320VC5401 датащи(PDF) 23 Page - Texas Instruments

TMS320VC5401 датащи(HTML) 23 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

датащи скачать

ссылки URL