TMS320VC5401 datasheet(74/81 Pages) TI

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Electrical Specifications

December 2000 − Revised February 2004

SPRS153C

Table 5−30. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)†

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(BDRV-BCKXH)

Setup time, BDR valid before BCLKX high

2 − 12H

th(BCKXH-BDRV)

Hold time, BDR valid after BCLKX high

5 + 12H

tsu(BFXL-BCKXL)

Setup time, BFSX low before BCLKX low

tc(BCKX)

Cycle time, BCLKX

12H

32H

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 5−31. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)†

PARAMETER

MASTER‡

SLAVE

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

th(BCKXH-BFXL)

Hold time, BFSX low after BCLKX high§

T − 5

T + 6

td(BFXL-BCKXL)

Delay time, BFSX low to BCLKX low¶

D − 7

D + 5

td(BCKXL-BDXV)

Delay time, BCLKX low to BDX valid

−4

6H + 3 10H + 17

tdis(BCKXH-BDXHZ)

Disable time, BDX high impedance following last data bit from

BCLKX high

D − 4

D + 5

tdis(BFXH-BDXHZ)

Disable time, BDX high impedance following last data bit from BFSX

high

2H + 2

6H + 19

td(BFXL-BDXV)

Delay time, BFSX low to BDX valid

4H − 4

8H + 19

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡ T = BCLKX period = (1 + CLKGDV) * 2H

D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

tsu(BFXL-BCKXL)

th(BCKXH-BDRV)

tdis(BFXH-BDXHZ)

tdis(BCKXH-BDXHZ)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

BCLKX

BFSX

BDX

BDR

td(BFXL-BCKXL)

td(BFXL-BDXV)

td(BCKXL-BDXV)

tsu(BDRV-BCKXH)

th(BCKXH-BFXL)

LSB

MSB

tc(BCKX)

Figure 5−26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

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