VT82C596 datasheet(84/96 Pages) ETC

84 / 96 page

VT82C596B

Revision 0.3 June 17, 1999

-78-

Functional Descriptions

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FUNCTIONAL DESCRIPTIONS

Power Management

ower Management Subsystem Overview

The power management function of the VT82C596B is

indicated in the following block diagram:

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Figure 6. Power Management Subsystem Block Diagram

Refer to ACPI Specification v1.0 and APM specification v1.2

for additional information.

Processor Bus States

The VT82C596B supports the complete set of C0 to C3

processor states as specified in the Advanced Configuration

and Power Interface (ACPI) specification (and defined in

ACPI I/O space Registers 10-15):

C0:

Normal Operation

C1:

CPU Halt (controlled by software).

C2:

Stop Clock. Entered when the P_LVL2 register is

read. The STPCLK# signal is asserted to put the

processor in the Stop Grant State. If the SRAM_ZZ

bit is set to 1, then the ZZ pin is also asserted (after

the acknowledgement of the stop grant bus cycle) for

powering down the cache SRAM.

The CPUSTP#

signal is not asserted so that host clocks remain

running. To exit this state, the chip negates the ZZ

signal and then negates STPCLK#.

C3:

Suspend. Entered when the P_LVL3 register is read.

In addition to STPCLK# and ZZ assertion as in the

C2 state, the SUSST1# (suspend status 1) signal is

asserted to tell the north bridge to switch to “Suspend

DRAM Refresh” mode based on the 32KHz suspend

clock (SUSCLK) provided by the VT82C596B. If

the HOST_STP bit is enabled, then CPUSTP# is also

asserted to stop clock generation and put the CPU

into Stop Clock State.

To exit this state, the chip

negates CPUSTP# and allows time for the processor

PLL to lock. Then the SUSST1#, ZZ, and STPCLK#

signals are negated to resume to normal operation.

During normal operation, two mechanisms are provided to

modulate CPU execution and control power consumption by

throttling the duty cycle of STPCLK#:

Setting the THT_EN bit to 1, the duty cycle

defined in THT_DTY (IO space Rx10) is used.

THRM# pin assertion enables automatic clock

throttling with duty cycle pre-configured in

THM_DTY (PCI configuration Rx4C).

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