VT82C596 datasheet(55/96 Pages) ETC

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VT82C596B

Revision 0.3 June 17, 1999

-49-

Function 1 Registers - Enhanced IDE Controller

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IDE-Controller-Specific Confiiguration Registers

Offset 40 - Chip Enable.....................................................RW

7-4

Reserved

........................................ always reads 0

3-2

Reserved (Do Not Program)...........R/W, default = 0

Primary Channel Enable........ default = 0 (disabled)

Secondary Channel Enable .... default = 0 (disabled)

Offset 41 - IDE Configuration..........................................RW

Primary IDE Read Prefetch Buffer

Disable ...................................................default

1Enable

Primary IDE Post Write Buffer

Disable ...................................................default

1Enable

Secondary IDE Read Prefetch Buffer

Disable ...................................................default

1Enable

Secondary IDE Post Write Buffer

Disable ...................................................default

1Enable

Reserved (Do Not Change)........................ default=0

Reserved (Do Not Change)........................ default=1

Reserved (Do Not Change)........................ default=0

Offset 42 - Reserved (Do Not Program) ..........................RW

7-2

Reserved

........................................ always reads 0

1-0

Reserved (Do Not Program).................... default = 0

Offset 43 - FIFO Configuration....................................... RW

7-4

Reserved

........................................ always reads 0

3-2

Threshold for Primary Channel

00 1

01 1/4

10 1/2

.................................................... default

11 3/4

1-0

Threshold for Secondary Channel

00 1

01 1/4

10 1/2

.................................................... default

11 3/4

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