VT82C596 datasheet(43/96 Pages) ETC

43 / 96 page

VT82C596B

Revision 0.3 June 17, 1999

-37-

PCI Function 0 Registers - PCI-to-ISA Bridge

7HFKQRORJLHV ,QF

:H &RQQHFW

Offset 43 - ROM Decode Control ....................................RW

Setting these bits enables the indicated address range to be

included in the ROMCS# decode:

FFFE0000h-FFFEFFFFh .......................... default=0

FFF80000h-FFFDFFFFh ......................... default=0

FFF00000h-FFF7FFFFh (new)................. default=0

000E0000h-000EFFFFh (new) .................. default=0

000E8000h-000EFFFFh (old).................... default=0

000E0000h-000E7FFFh (old) .................... default=0

000D8000h-000DFFFFh ........................... default=0

000D0000h-000D7FFFh ............................ default=0

000C8000h-000CFFFFh ........................... default=0

000C0000h-000C7FFFh............................. default=0

Offset 44 - Keyboard Controller Control........................RW

KBC Timeout Test (do not program) ....... default = 0

6-4

Reserved (do not program)........................ default = 0

Mouse Lock Enable

Disabled .................................................default

1Enabled

2-1

Reserved (do not program)........................ default = 0

Reserved (no function) .............................. default = 0

Offset 45 - Type F DMA Control .....................................RW

ISA Master / DMA to PCI Line Buffer.... default=0

DMA type F Timing on Channel 7 ........... default=0

DMA type F Timing on Channel 6 ........... default=0

DMA type F Timing on Channel 5 ........... default=0

DMA type F Timing on Channel 3 ........... default=0

DMA type F Timing on Channel 2 ........... default=0

DMA type F Timing on Channel 1 ........... default=0

DMA type F Timing on Channel 0 ........... default=0

Offset 46 - Miscellaneous Control 1 ................................ RW

PCI Master Write Wait States

0 Wait States.......................................... default

1 Wait State

6Gate INTRQ

Disable................................................... default

1Enable

Flush Line Buffer for Int or DMA IOR Cycle

Disable................................................... default

1Enable

Config Command Reg Rx04 Access (Test Only)

Normal: Bits 0-1=RO, Bit 3=RW ......... default

Test Mode: Bits 0-1=RW, Bit-3=RO

Reserved (do not program) ........................ default = 0

Reserved (no function) .............................. default = 0

PCI Burst Read Interruptability

Allow burst reads to be interrupted........ default

Don’t allow PCI burst reads to be interrupted

Post Memory Write Enable

Disable................................................... default

1Enable

The Post Memory Write function is automatically

enabled when Delay Transaction (see Rx47 bit-6

below) is enabled, independent of the state of this bit.

Offset 47 - Miscellaneous Control 2 ................................ RW

CPU Reset Source

Use CPURST as CPU Reset .................. default

Use INIT as CPU Reset

PCI Delay Transaction Enable

Disable................................................... default

1Enable

The "Post Memory Write" function is automatically

enabled when this bit is enabled, independent of the

state of Rx46 bit-0 above.

EISA 4D0/4D1 Port Enable

Disable (ignore ports 4D0-1) ................. default

Enable (ports 4D0-1 per EISA specification)

Interrupt Controller Shadow Register Enable

Disable................................................... default

1Enable

Reserved (always program to 0).............. default = 0

Note: Always mask this bit. This bit may read back

as either 0 or 1 but must always be

programmed with 0.

Write Delay Transaction Time-Out Timer Enable

Disable................................................... default

1Enable

Read Delay Transaction Time-Out Timer Enable

Disable................................................... default

1Enable

Software PCI Reset ...... write 1 to generate PCI reset

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