VT82C596 datasheet(81/96 Pages) ETC

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VT82C596B

Revision 0.3 June 17, 1999

-75-

Function 3 Registers - Power Management and SMBus

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I/O Offset 2D-2C - Global Control (GBL_CTL) ............RW

15-12 Reserved

........................................ always reads 0

IDE Secondary Bus Power Off

Disable ...................................................default

1Enable

IDE Primary Bus Power Off

Disable ...................................................default

1Enable

Reserved

........................................ always reads 0

SMI Active (INSMI)

SMI Inactive...........................................default

SMI Active. If the SMIIG bit is set, this bit

needs to be written with a 1 to clear it before

the next SMI can be generated.

LID Triggering Polarity

Rising Edge ............................................default

Falling Edge

THRM# Triggering Polarity

Rising Edge ............................................default

Falling Edge

Disable Battery Low Resume

Enable resume ........................................default

Disable

resume

from

suspend

when

BATLOW# is asserted

SMI Lock (SMIIG)

Disable SMI Lock

Enable SMI Lock (SMI low to gate for the

next SMI) ...............................................default

Wait for Halt / Stop Grant Cycle for STPCLK#

Assertion

Don’t wait...............................................default

1Wait

This bit works with Rx4C[7] of PCI configuration

space to control the start of STPCLK# assertion.

Power Button Triggering

SCI/SMI generated by PWRBTN# rising edge

SCI/SMI generated by PWRBTN# low level

Must be set to 1 for ACPI v0.9 compliance.

BIOS Release (BIOS_RLS)

This bit is set by legacy software to indicate release

of the SCI/SMI lock.

Upon setting of this bit,

hardware automatically sets the GBL_STS bit. This

bit is cleared by hardware when the GBL_STS bit

cleared by software.

Note that if the GBL_EN bit is set (bit-5 of the Power

Management Enable register at offset 2), then setting

this bit causes an SCI to be generated (because setting

this bit causes the GBL_STS bit to be set).

SMI Enable (SMI_EN)

Disable all SMI generation

Enable SMI generation

I/O Offset 2F - SMI Command (SMI_CMD) ................. RW

7-0

SMI Command

Writing to this port sets the SW_SMI_STS bit. Note

that if the SW_SMI_EN bit is set (see bit-6 of the

Global Enable register at offset 2Ah), then an SMI is

generated.

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