TMS320VC5509 datasheet(23/122 Pages) TI

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Introduction

April 2001 − Revised September 2004

SPRS163G

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

BK‡

FUNCTION

I/O/Z†

MULTIPLEXED

SIGNAL NAME

PARALLEL BUS (CONTINUED)

C13

I/O/Z

SDRAM A10 address line or general-purpose IO13. This pin serves in one

of two functions: SDRAM A10 address line (EMIF.SDA10) or

general-purpose IO13 (GPIO13). The initial state of this pin depends on

the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.SDA10

O/Z

SDRAM A10 address line. Address line/autoprecharge disable for

SDRAM memory. Serves as a row address bit (logically equivalent to A12)

during ACTV commands and also disables the autoprecharging function

of SDRAM during read or write operations. EMIF.SDA10 is selected when

the Parallel Port Mode bit field of the External Bus Selection Register is set

to 00 or 01.

Output,

EMIF.SDA10

GPIO0 = 0:

Input,

GPIO13

I/O/Z

General-purpose IO13. GPIO13 is selected when the Parallel Port Mode

bit field is set to 10 or 11.

C14

I/O/Z

Memory interface clock for SDRAM, HPI Data Strobe 2 input, or

general-purpose IO14. This pin serves in one of two functions: memory

interface clock for SDRAM (EMIF.CLKMEM) or HPI data strobe 2

(HPI.HDS2). The initial state of this pin depends on the GPIO0 pin. See

Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.CLKMEM

O/Z

Memory interface clock for SDRAM. EMIF.CLKMEM is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is set to

00 or 01.

EMIF.CLKMEM

GPIO0 = 0:

Input,

HPI.HDS2

HPI Data Strobe 2 Input. HPI.HDS2 is driven by the host read or write

strobes to control the transfer. HPI.HDS2 is selected when the Parallel

Port Mode bit field is set to 10 or 11.

Input,

HPI.HDS2

INTERRUPT AND RESET PINS

INT[4:0]

Active-low external user interrupt inputs. INT[4:0] are maskable and are

prioritized by the interrupt enable register (IER) and the interrupt mode bit.

Input

RESET

Active-low reset. RESET causes the digital signal processor (DSP) to

terminate execution and forces the program counter to FF8000h. When

RESET is brought to a high level, execution begins at location FF8000h of

program memory. RESET affects various registers and status bits. Use an

external pullup resistor on this pin.

Input

† I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡ BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer

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