TMS320VC5509 datasheet(13/122 Pages) TI

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Introduction

April 2001 − Revised September 2004

SPRS163G

The TMS320C55x DSP core was created with an open architecture that allows the addition of

application-specific hardware to boost performance on specific algorithms. The hardware extensions on the

5509 strike the perfect balance of fixed function performance with programmable flexibility, while achieving

low-power consumption, and cost that traditionally has been difficult to find in the video-processor market. The

extensions allow the 5509 to deliver exceptional video codec performance with more than half its bandwidth

available for performing additional functions such as color space conversion, user-interface operations,

security, TCP/IP, voice recognition, and text-to-speech conversion. As a result, a single 5509 DSP can power

most portable digital video applications with processing headroom to spare. For more information, see the

TMS320C55x Hardware Extensions for Image/Video Applications Programmer’s Reference (literature

number SPRU098). For more information on using the the DSP Image Processing Library, see the

TMS320C55x Image/Video Processing Library Programmer’s Reference (literature number SPRU037).

2.2

Pin Assignments

Figure 2−1 illustrates the ball locations for the 179-pin ball grid array (BGA) package and is used in conjunction

with Table 2−1 to locate signal names and ball grid numbers. DVDD is the power supply for the I/O pins while

CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

2.2.1 Terminal Assignments for the GHH Package

12 13

10 11

8 9

Figure 2−1. 179-Terminal GHH Ball Grid Array (Bottom View)

TMS320VC5509 датащи(PDF) 13 Page - Texas Instruments