TMS320VC5509 datasheet(78/122 Pages) TI

78 / 122 page

Electrical Specifications

April 2001 − Revised September 2004

SPRS163G

5.6.2 Layout Considerations

Since parasitic capacitance, inductance and resistance can be significant in any circuit, good PC board layout

practices should always be observed when planning trace routing to the discrete components used in the

oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close

to the DSP as physically possible. Also, X1 and X2/CLKIN traces should be separated as soon as possible

after routing away from the DSP to minimize parasitic capacitance between them, and a ground trace should

be run between these two signal lines. This also helps to minimize stray capacitance between these two

signals.

5.6.3 Clock Generation in Bypass Mode (DPLL Disabled)

The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of one, two, or

four to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock

mode register. The contents of this field only affect clock generation while the device is in bypass mode. In

this mode, the digital phase-locked loop (DPLL) clock synthesis is disabled.

Table 5−3 and Table 5−4 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5−3).

Table 5−3. CLKIN Timing Requirements

NO.

MIN

MAX

UNIT

tc(CI)

Cycle time, X2/CLKIN

400†

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

C10

tw(CIL)

Pulse duration, CLKIN low

C11

tw(CIH)

Pulse duration, CLKIN high

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. If an external crystal is used, the X2/CLKIN cycle

time is limited by the crystal frequency range listed in Table 5−2.

Table 5−4. CLKOUT Switching Characteristics

NO.

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

20‡

D*tc(CI)§

1600†

td(CIH-CO)

Delay time, X2/CLKIN high to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H−2

H+2

tw(COH)

Pulse duration, CLKOUT high

H−2

H+2

† This device utilizes a fully static design and therefore can operate with tc(CO) approaching ∞. If an external crystal is used, the X2/CLKIN cycle

time is limited by the crystal frequency range listed in Table 5−2.

‡ It is recommended that the DPLL synthesised clocking option be used to obtain maximum operating frequency.

§ D = 1/(PLL Bypass Divider)

TMS320VC5509 датащи(PDF) 78 Page - Texas Instruments

TMS320VC5509 датащи(HTML) 78 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL