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AN983 датащи(PDF) 34 Page - List of Unclassifed Manufacturers |
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AN983 датащи(HTML) 34 Page - List of Unclassifed Manufacturers |
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34 / 91 page ![]() AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY 0: filters all bad packets 2 --- Reserved 1 SR Start/Stop Receive 0: receive processor will enter stop state after the current reception frame completed. This value is effective only when the receive processor is in the running or suspending state. Notice: In “Stop Receive” state, the PAUSE packet and Remote Wake Up packet won’t be affected and can be received if the corresponding function is enabled. 1: receive processor will enter running state. 0 R/W 0 --- Reserved W* = only write when the transmit processor stopped. W** = only write when the transmit and receive processor both stopped. W*** = only write when the receive processor stopped. CSR7 (offset = 38h), IER - Interrupt Enable Register Bit # Name Descriptions (Refer to CSR5) Default Val RW Type 31~17 --- Reserved 16 NIE Normal Interrupt Enable 1: enable all the normal interrupt bits (see bit16 of CSR5) 0 R/W 15 AIE Abnormal Interrupt Enable 1: enable all the abnormal interrupt bits (see bit 15 of CSR5) 0 R/W 14 --- Reserved 13 FBEIE Fatal Bus Error Interrupt Enable 1: combine this bit and bit 15 of CSR7 to enable fatal bus error interrupt 0 R/W 12 11 GPTIE General Purpose Timer Interrupt Enable 1: combine this bit and bit 15 of CSR7 to enable general-purpose timer expired interrupt. 0 R/W 10 9 RWTIE Receive Watchdog Time-out Interrupt Enable 1: combine this bit and bit 15 of CSR7 to enable receive watchdog time-out interrupt. 0 R/W 8 RSIE Receive Stopped Interrupt Enable 1: combine this bit and bit 15 of CSR7 to enable receive stopped interrupt. 0 R/W 7 RUIE Receive Descriptor Unavailable Interrupt Enable 1: combine this bit and bit 15 of CSR7 to enable receive descriptor unavailable interrupt. 0 R/W 6 RCIE Receive Completed Interrupt Enable 0 R/W ADMtek Inc. www.admtek.com.tw Rev. 1.8 34 |
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