DP83902A datasheet(22/70 Pages) NSC

22 / 70 page

80 Packet Transmission

The Local DMA is also used during transmission of a pack-

et Three registers control the DMA transfer during trans-

mission a Transmit Page Start Address Register (TPSR)

and the Transmit Byte Count Registers (TBCR0 1) When

the ST-NIC receives a command to transmit the packet

pointed to by these registers buffer memory data will be

moved into the FIFO as required during transmission The

ST-NIC will generate and append the preamble synch and

CRC fields

General Transmit Packet Format

Transmit

Destination Address

6 Bytes

Byte

Source Address

6 Bytes

Count

TypeLength

2 Bytes

TBCR0 1

Data

Pad (If Data k 46 Bytes)

46 Bytes

TRANSMIT PACKET ASSEMBLY

The ST-NIC requires a contiguous assembled packet with

the format shown The transmit byte count includes the

Destination Address Source Address Length Field and

Data It does not include preamble and CRC When trans-

mitting data smaller than 46 bytes the packet must be pad-

ded to a minimum size of 64 bytes The programmer is re-

sponsible for adding and stripping pad bytes

TRANSMISSION

Prior to transmission the TPSR (Transmit Page Start Regis-

ter) and TBCR0 TBCR1 (Transmit Byte Count Registers)

must be initialized To initiate transmission of the packet the

TXP bit in the Command Register is set The Transmit

Status Register (TSR) is cleared and the ST-NIC begins to

prefetch transmit data from memory (unless the ST-NIC is

currently receiving) If the interframe gap has timed out the

ST-NIC will begin transmission

CONDITIONS REQUIRED TO BEGIN TRANSMISSION

In order to transmit a packet the following three conditions

must be met

1 The Interframe Gap Timer has timed out the first 64 ms

of the Interframe Gap

2 At least one byte has entered the FIFO (This indicates

that the burst transfer has been started)

3 If a collision has been detected the backoff timer has

expired

In typical systems the ST-NIC prefetchs the first burst of

bytes before the 64 ms timer expires The time during which

ST-NIC transmits preamble can also be used to load the

FIFO

Note

If carrier sense is asserted before a byte has been loaded into the

FIFO the ST-NIC will become a receiver

COLLISION RECOVERY

During transmission the Buffer Management logic monitors

the transmit circuitry to determine if a collision has occurred

If a collision is detected the Buffer Management logic will

reset the FIFO and restore the Transmit DMA pointers for

retransmission of the packet The COL bit will be set in the

TSR and the NCR (Number of Collisions Register) will be

incremented If 15 retransmissions each result in a collision

the transmission will be aborted and the ABT bit in the TSR

will be set

Note

NCR reads as zeroes if excessive collisions are encountered

TRANSMIT PACKET ASSEMBLY FORMAT

The following diagrams describe the format for how packets

must be assembled prior to transmission for different byte

ordering schemes The various formats are selected in the

Data Configuration Register

D15

D8 D7

Destination Address 1

Destination Address 0

Destination Address 3

Destination Address 2

Destination Address 5

Destination Address 4

Source Address 1

Source Address 0

Source Address 3

Source Address 2

Source Address 5

Source Address 4

TypeLength 1

TypeLength 0

Data 1

Data 0

BOS e 0 WTS e 1 in Data Configuration Register

This format is used with Series 32xxx or 808xx processors

D15

D8 D7

Destination Address 0

Destination Address 1

Destination Address 2

Destination Address 3

Destination Address 4

Destination Address 5

Source Address 0

Source Address 1

Source Address 2

Source Address 3

Source Address 4

Source Address 5

TypeLength 0

TypeLength 1

Data 0

Data 1

BOS e 1 WTS e 1 in Data Configuration Register

This format is used with 680x0 type processors

Destination Address 0

Destination Address 1

Destination Address 2

Destination Address 3

Destination Address 4

Destination Address 5

Source Address 0

Source Address 1

Source Address 2

Source Address 3

Source Address 4

Source Address 5

BOS e 0 WTS e 0 in Data Configuration Register

This format is used with general 8-bit processors

Note

All examples above will result in a transmission of a packet in order of

DA0 DA1 DA2 DA3

bits within each byte will be transmitted

least significant bit first

DA e Destination Address

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