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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83902A датащи(PDF) 52 Page - National Semiconductor (TI) |
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DP83902A датащи(HTML) 52 Page - National Semiconductor (TI) |
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52 / 70 page  150 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary Register Read (Latched Using ADS0) TLF11157 – 33 Symbol Parameter Min Max Units rss Register Select Setup to ADS0 Low 10 ns rsh Register Select Hold from ADS0 Low 13 ns aswi Address Strobe Width In 15 ns ackdv Acknowledge Low to Data Valid 55 ns rdz Read Strobe to Data TRI-STATE (Note 3) 15 70 ns rackl Read Strobe to ACK Low (Notes 1 2) n bcyc a 30 ns rackh Read Strobe to ACK High 30 ns rsrsl Register Select to Slave Read Low 10 ns Latched RS0 – 3 Note 1 ACK is not generated until CS and SRD are low and the ST-NIC has synchronized to the register access The ST-NIC will insert an integral number of Bus Clock cycles until it is synchronized In Dual Bus systems additional cycles will be used for a local or remote DMA to complete Wait states must be issued to the CPU until ACK is asserted low Note 2 CS may be asserted before or after SRD IfCS is asserted after SRD rackl is referenced from falling edge of CS CS can be de-asserted concurrently with SRD or after SRD is de-asserted Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with no contention 52 |
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