DP83902A datasheet(57/70 Pages) NSC

номер детали	DP83902A

подробное описание детали	ST-NICTM Serial Network Interface Controller for Twisted Pair

PDF	70 Pages

Scroll/Zoom	100%

производитель	NSC [National Semiconductor (TI)]

домашняя страница	http://www.national.com

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57 / 70 page

150 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued)

DMA Address Generation

TLF11157 – 38

Symbol

Parameter

Min

Max

Units

bcyc

Bus Clock Cycle Time (Note 2)

125

bch

Bus Clock High Time

bcl

Bus Clock Low Time

bcash

Bus Clock to Address Strobe High

bcasl

Bus Clock to Address Strobe Low

aswo

Address Strobe Width Out

bch

bcadv

Bus Clock to Address Valid

bcadz

Bus Clock to Address TRI-STATE (Note 3)

ads

Address Setup to ADS01 Low

bch b 15

adh

Address Hold from ADS01 Low

bcl b 5ns

Note 1

Cycles T1 T2 T3 and T4 are only issued for the first transfer in a burst when 32-bit mode has been selected

Note 2

The rate of bus clock must be high enough to support transfers tofrom the FIFO at a rate greater than the serial network transfers fromto the FIFO

Note 3

These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with

no contention

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