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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83902A датащи(PDF) 60 Page - National Semiconductor (TI) |
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DP83902A датащи(HTML) 60 Page - National Semiconductor (TI) |
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60 / 70 page  150 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Wait State Insertion TLF11157 – 41 Symbol Parameter Min Max Units ews External Wait Setup to T3 0Clock (Note 1) 10 ns ewr External Wait Release Time (Note 1) 15 ns Note 1 The addition of wait states affects the count of deserialized bytes and is limited to a number of bus clock cycles depending on the bus clock and network rates The allowable wait states are found in the table below (Assumes 10 Mbitsec data rate) BSCK (MHz) Max of Wait States Byte Transfer Word Transfer 80 1 10 0 1 12 1 2 14 1 2 16 1 3 18 2 3 20 2 4 Table assumes 10 MHz network clock The number of allowable wait states in byte mode can be calculated using W(byte mode) e 8tnw 45 tbsck b 1 J W e Number of Wait States tnw e Network Clock Period tbsck e BSCK Period The number of allowable wait states in word mode can be calculated using W(word mode) e 5tnw 2 tbsck b 1 J 60 |
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