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DP83902A датащи(PDF) 29 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали DP83902A
подробное описание детали  ST-NICTM Serial Network Interface Controller for Twisted Pair
PDF  70 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83902A датащи(HTML) 29 Page - National Semiconductor (TI)

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100 Internal Registers (Continued)
103 REGISTER DESCRIPTIONS
(Continued)
DATA CONFIGURATION REGISTER (DCR)
0EH (WRITE)
This Register is used to program the ST-NIC for 8- or 16-bit memory interface select byte ordering in 16-bit applications and
establish FIFO thresholds The DCR must be initialized prior to loading the Remote Byte Count Registers LAS is set on
power up
76543210
FT1
FT0
ARM
LS
LAS
BOS
WTS
Bit
Symbol
Description
D0
WTS
Word Transfer Select
0 Selects byte-wide DMA transfers
1 Selects word-wide DMA transfers
WTS establishes byte or word transfers for both Remote and Local DMA transfers
Note
When word-wide mode is selected up to 32k words are addressable A0 remains low
D1
BOS
Byte Order Select
0 MS byte placed on AD15 – AD8 and LS byte on AD7 – AD0 (32xxx 80x86)
1 MS byte placed on AD7 – AD0 and LS byte on AD15 – A8 (680x0)
Ignored when WTS is low
D2
LAS
Long Address Select
0 Dual 16-bit DMA mode
1 Single 32-bit DMA mode
When LAS is high the contents of the Remote DMA registers RSAR0 1 are issued as A16 – A31 Power up
high
D3
LS
Loopback Select
0 Loopback mode selected Bits D1 and D2 of the TCR must also be programmed for Loopback operation
1 Normal Operation
D4
ARM
Auto-Initialize Remote
0 Send Command not executed all packets removed from Buffer Ring under program control
1 Send Command executed Remote DMA auto-initialized to remove packets from Buffer Ring
Note
Send Command cannot be used with 680x0 byte processors
D5
FT0
FIFO Threshold Select
Encoded FIFO threshold Establishes point at which bus is requested when filling or
emptying the FIFO During reception the FIFO threshold indicates the number of bytes (or words) the FIFO has
and
and
filled serially from the network before bus request (BREQ) is asserted
D6
FT1
Note
FIFO threshold setting determines the DMA burst length
Receive Thresholds
FT1
FT0
Word Wide
Byte Wide
0
0
1 Word
2 Bytes
0
1
2 Words
4 Bytes
1
0
4 Words
8 Bytes
1
1
6 Words
12 Bytes
During transmission the FIFO threshold indicates the number of bytes (or words) the FIFO has filled from the
Local DMA before BREQ is asserted Thus the transmission threshold is 13 bytes minus the received
threshold
29



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