AD9531 datasheet(33/88 Pages) AD

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Data Sheet

AD9531

LOOP

FILTER

3.3V

VCO

÷N1B

REF1_Ax

REF1_Bx

OUT1_0x

OUT1_9x

REF1_SEL

RFIN1x

AD9531: PLL1

REFERENCE

INPUT

LDO

REG 1

Figure 16. PLL1 Loop 3 Configuration

LOOP

FILTER

VCO

÷M1

REF1_Ax

REF1_Bx

OUT1_0x

OUT1_9x

REF1_SEL

RFIN1x

AD9531: PLL1

1.8V

REFERENCE

INPUT

LDO

REG 1

Figure 17. PLL1 Internal Loop 4 Configuration

PLL1 Loop 3 Configuration (External VCXO)

The Loop 3 configuration enables the RFIN receiver and the

3.3 V charge pump. Note that an external loop filter is required

between the LF pin and the control input of the external VCXO.

The VCXO frequency is a function of the PFD input frequency

(see the PLL1 Reference Frequency Scaling section) and the

value programmed into the register associated N1B.

fVCXO = fPFD × N1B

where N1B is an element of the following set: {1, 4, 5 ... 4,095}.

The overall frequency translation equation for Loop 3 is as follows:

N1B

REF

OUT

where:

fOUT1 is the frequency at OUT1_x.

fREF is the frequency of the active reference (REF_1A or REF_1B).

R1 is an element of the following set: {½, 1, 4, 5 ... 4,095}. The

value of ½ is the result of selecting the ×2 reference multiplier

(by programming the R1 divider to a value of 0).

D1 is the channel divider (D1A, D1B, or D1C) associated with

OUT1_x and is also an element of the following set: {1, 2 ... 256}.

PLL1 Loop 4 Configuration (Integrated VCO or External

VCXO)

The Loop 4 configuration has two variants: internal and external.

The internal configuration uses the internal VCO, whereas the

external configuration relies on an external VCXO. Note that the

Loop 4 configuration bypasses the N1B divider, which the block

diagram of PLL1 (see Figure 12) does not explicitly show.

The Loop 4 configuration provides a fixed delay function,

which results from the channel dividers being synchronized to

each other and the input to the PFD originating from one of the

output drivers (per Register 0x0101, Bits[D6:D5]). That is, the

feedback reference point of the PLL is one of the outputs, which

yields the fixed delay function. The fixed delay function effectively

edge aligns all the outputs (OUT1_x) with the reference input

because, by design, the internal delay of the reference path closely

matches the internal feedback delay from the channel dividers.

Internal Loop 4 Configuration

In the internal Loop 4 configuration, the feedback divider

consists of M1 and one of the channel dividers (D1A, D1B, or

D1C) in cascade. The particular channel divider included in the

feedback path depends on the fixed delay bits per Table 57.

fVCO = fPFD × (M1 × D1)

where:

M1 is an element of the following set: {3, 4 ... 11}.

D1 is the channel divider (D1A, D1B, or D1C) associated with

OUT1_x. D1 is also an element of the following set: {1, 2 ... 256}.

The overall frequency translation equation for Loop 4 using the

internal VCO is as follows:

REF

OUT1

where:

fOUT1 is the frequency at OUT1_x.

fREF is the frequency of the active reference (REF_1Ax or REF_1Bx).

R1 is an element of the following set: {½, 1, 4, 5 ... 4,095}. The

value of ½ is the result of selecting the ×2 reference multiplier

(by programming the R1 divider to a value of 0).

Note that internal Loop 4 configuration still allows calibration

of the internal VCO, but requires special treatment (see the

PLL1 Internal VCO Calibration section).

Rev. 0 | Page 33 of 88

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