AD9531 datasheet(12/88 Pages) AD

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AD9531

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

3.3 V CHARGE PUMP CURRENT

These charge pump specifications are only applic-

able to the 3.3 V charge pump, which draws its

power from Pin 23 (VDD1_3V3)

ICP Sink/Source

Programmable via Register 0x0101, Bits[D4:D2]

Highest Programmable Value

±5.0

Lowest Programmable Value

±0.625

ICP High Impedance Mode Leakage

0.5

Sink and Source Current Matching

0.8 V < VCP < VDD − 0.8 V

ICP vs. VCP

0.8 V < VCP < VDD − 0.8 V

ICP vs. Temperature

VCP = VDD/2

PLL FIGURE OF MERIT (FOM)

−221

dBc/Hz

Applies to wide loop bandwidth mode (see the PLL1

Loop 2 Wide Bandwidth Configuration section)

measured at 500 kHz offset relative to the output

frequency under the following conditions: fR =

245.76 MHz (differential input), fOUT = 122.88 MHz

(HSTL output), integer-N PLL mode, internal VCO,

and loop bandwidth = 500 kHz

PLL1 RFIN1_x Inputs

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL MODE

Input Frequency Range

400

MHz

Input Sensitivity

200

mV p-p

Capacitive coupling recommended

Input Slew Rate

100

V/µs

Minimum limit imposed for jitter performance (when using a

sinusoidal source, for example)

Common-Mode Internally

Generated Bias Voltage

0.65

Differential Input Resistance

5.6

kΩ

Differential Input Capacitance

CMOS MODE, SINGLE-ENDED INPUT

Input Frequency Range

400

MHz

Input Voltage

High

1.2

Low

0.6

Hysteresis

300

Input Resistance

MΩ

Input Capacitance

PLL1 Jitter Generation

The jitter integration bandwidth is from 12 kHz to 20 MHz.

Table 15.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ABSOLUTE TIME JITTER

Fractional Mode

0.462

ps rms

fR = 10 MHz, fOUT = 122.88 MHz, fLOOP = 90 kHz

Integer Mode

0.360

ps rms

fR = 15.36 MHz, fOUT = 122.88 MHz, fLOOP = 100 kHz

Wide Loop Bandwidth Integer Mode1

0.204

ps rms

fR = 122.88 MHz, fOUT = 122.88 MHz, fLOOP = 300 kHz

External VCXO Mode

0.145

ps rms

fR = 10 MHz, fOUT = 122.88 MHz, fLOOP = 100 Hz

ADDITIVE TIME JITTER

Additive jitter contribution is from the RFIN1_x input

to the OUT_x output, excluding the VCXO contribution

External VCXO Mode

0.125

ps rms

fVCXO = 122.88 MHz, fOUT = 122.88 MHz

See the PLL1 Loop 2 Wide Bandwidth Configuration section.

Rev. 0 | Page 12 of 88

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