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AD9531

Data Sheet

Address

Bits

Bit Name

Description

[D2:D1]

REF1A input mode

[1:0]

These bits set the configuration of the REF1_A input reference.

00: differential input (REF1_AP/REF1_AN inputs active).

01: 3.3 V CMOS single-ended (REF1_AP active, REF1_AN disabled).

10: not applicable.

11: 2.5 V CMOS single-ended (REF1_AP active, REF1_AN disabled).

REF1A power-down

Logic 1 powers down the REF1_AP/REF1_AN inputs.

PLL1 Frequency Translation Registers—Register 0x0104 to Register 0x010F

Table 58. PLL1 Frequency Translation Register Details

Address

Bits

Bit Name

Description

0x0104

[D7:D0]

R1 [7:0]

R1 divider Bit D7 to Bit D0 (LSB). See Register 0x0105, Bits[D3:D0] for details.

0x0105

[D7:D4]

Unused

Unused.

[D3:D0]

R1 [11:8]

R1 divider Bit D11 (MSB) to Bit D8. The value of R1, Bits[D11:D0] results in the following behavior:

0: multiplies the input frequency by a factor of 2.

1 to 3: passes the input frequency unaltered (R1 divider bypass).

4 to 4095: divides the input frequency by this value.

0x0106

[D7:D0]

N1A [7:0]

N1A Bit D7 (MSB) to Bit D0 (LSB). The value of N1A [7:0] results in the following behavior,

depending on the operating mode (integer-N or fractional-N):

For integer-N mode,

0 to 14: not applicable.

15 to 255: divide by this value.

For fractional-N mode,

0 to 79: not applicable.

80 to 255: divide by this value.

0x0107

[D7:D0]

N1A fraction [7:0]

N1A Fraction Bit D7 to Bit D0 (LSB). See Register 0x0109, Bits[D3:D0] for details.

0x0108

[D7:D0]

N1A fraction [15:8]

N1A Fraction Bit D15 to Bit D8. See Register 0x0109, Bits[D3:D0] for details.

0x0109

[D7:D4]

Reserved

Reserved.

[D3:D0]

N1A fraction [19:16]

N1A Fraction Bit D19 (MSB) to Bit D16. The value of N1A fraction [19:0] results in the following

behavior:

0: enables integer mode (disables the Σ-Δ modulator).

1 to 1048574: enables fractional-N mode (Σ-Δ modulator active).

0x010A

[D7:D0]

N1A modulus [7:0]

N1A Modulus Bit D7 to Bit D0 (LSB). See Register 0x010C, Bits[D3:D0] for details.

0x010B

[D7:D0]

N1A modulus [15:8]

N1A Modulus Bit D8 to Bit D15. See Register 0x010C, Bits[D3:D0] for details.

0x010C

[D7:D4]

Reserved

Reserved.

[D3:D0]

N1A modulus [19:16]

N1A Modulus Bit D19 (MSB) to Bit D16. N1A Modulus [19:0] must be greater than N1A fraction

(1,048,575 maximum).

0x010D

[D7:D0]

N1B [7:0]

N1B Bit D7 to Bit D0 (LSB). See Register 0x010E, Bits[D3:D0] for details.

0x010E

[D7:D4]

Unused

Unused.

[D3:D0]

N1B [11:8]

N1B Bit D11 (MSB) to Bit D8. The value of N1B [11:0] results in the following behavior:

0 to 1: disallows the Loop 2 configuration and bypasses the N1B divider.

2 to 3: undefined.

4 to 4095: divides the by this value.

The Loop 4 configuration bypasses the N1B divider regardless of the value of N1B [11:0].

0x010F

[D7:D4]

Unused

Unused.

[D3:D0]

M1 [3:0]

M1 Bit D3 (MSB) to Bit D0. The value of the M1 [3:0] bits results in the following behavior:

0 to 2: disable.

3 to 11: divide by this value.

12 to 14: disables VCO calibration after changing the value of M1.

15: M1 divider reset state. If the user intends to change the M1 divider without performing a

subsequent PLL1 VCO calibration, then program this value (followed by an input/output update)

before programming the new M1 divider value (followed by an input/output update). An

input/output update is writing Register 0x0005, Bit D0 = 1. The procedure given here is unnecessary

if the user performs a PLL1.

Rev. 0 | Page 64 of 88

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