AD9531 datasheet(49/88 Pages) AD

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Data Sheet

AD9531

ADDITIONAL FEATURES

POWER-ON RESET (POR)

Applying power to the AD9531 causes an internal power-on

reset (POR) event. The POR event expires approximately 20 ms

after the supply voltages reach 80% of their nominal value. The

POR event allows the device to initialize to a known state at

power-up by initiating a ROM load sequence (see the ROM

Profiles section). Note that the POR event is critical to the

operation of the multifunction pins.

ROM PROFILES

The AD9531 has an integrated ROM partitioned into 64 groups.

Each group constitutes a ROM profile. Each ROM profile stores

data that maps to particular SPI registers and establishes the

depend on the current ROM profile selection. Therefore, the

ROM label for the default value is in the Register Map for those

registers mapped to the ROM.

At power-up, one of the first 16 ROM profiles is loaded into the

Pins (LDET1/M1, LDET2/M2, LDET3/M3, LOR/M4) section

for more information). However, the user can select any one of

the 64 possible ROM profiles by writing the desired profile value

(from 0 to 63) into Register 0x000E, Bits[D5:D0] (this register does

not require an input/output update). Writing to Register 0x000E

results in an immediate download of the ROM profile contents

into the register map and a reset of all PLLs. This reset means that

each PLL must be calibrated and synchronized (as applicable),

unless the ROM profile contains the requisite calibrate and sync

commands.

A listing of the register default values associated with each

ROM profile appears in the ROM Profile Data section.

Furthermore, reading Register 0x000E allows the user to obtain

the index value of the most recently loaded ROM profile.

MULTIFUNCTION PINS (LDET1/M1, LDET2/M2,

LDET3/M3, LOR/M4)

During a POR event, the LDET1/M1, LDET2/M2, LDET3/M3,

and LOR/M4 pins function as inputs and constitute four ROM

profile select pins. The logic level on these pins during the POR

event constitutes a 4-bit binary word, M4-M3-M2-M1, that selects

one of the first 16 ROM profiles, with M4 denoting the most

significant bit (MSB) and M1 the least significant bit (LSB). For

example, during a POR event, if the logic level on the pins, M4-

M3-M2-M1, is 0-1-0-0, respectively, then the AD9531

automatically loads ROM Profile 4.

Upon expiration of the POR event, the multifunction pins

revert from Mx inputs to LDETx and LOR outputs. Note that,

when the LDETx and LOR pins function as output signals, each pin

is independently capable of 1.8 V or 3.3 V CMOS logic levels. The

output logic level for each pin depends on its associated 3.3 V mode

bit in Register 0x0083 and Register 0x0084.

When configuring these multifunction pins for 3.3 V operation,

the pins make use of a booster circuit that generates 3.3 V from

internally available 1.8 V supply domains. This generation has

an impact on the 3.3 V operating mode of the LOR/M1 pin in

particular, as it requires PLL2 to be active (powered up). The

reason for this requirement is that the LOR/M1 pin uses the

internal 1.8 V supply domain associated with PLL2. Therefore,

powering down PLL2 shuts down the 1.8 V source that supplies

the booster circuit of the LOR/M1 pin. Furthermore, when

operating the LOR or LDETx pins in 3.3 V mode, it is best to

program the logical sense of the pin such that it is normally in a

Logic 0 state. That is, when using the LOR pin in 3.3 V mode,

program the pin to produce Logic 0 during normal operation

(when an LOR condition does not exist). Likewise, when using

the LDETx pins in 3.3 V mode, program them to produce Logic 0

during normal operation (when a lock condition exists).

Using the Mx Pins with 1.8 V, 3.3 V, or 1.5 V CMOS Logic

A functional diagram of a representative Mx pin is shown in

Figure 25. During a POR event (see the Power-On Reset (POR)

section), S1 is in the POR position, which connects each Mx pin

to its own internal 1.8 V CMOS receiver. After a POR event, S1

is in the NORM position, which connects each Mx pin to its

own internal CMOS driver (capable of either 1.8 V or 3.3 V

logic levels, per Register 0x0083 and Register 0x0084).

Therefore, except for the brief interval of time during a POR

event, the Mx pins operate with S1 in the NORM position,

which constitutes normal device operation.

POR

NORM

AD9531

1.8V

Figure 25. Functional Diagram of an Mx Pin

See the Interfacing to the Multifunction Pins section in the

Applications Information section for details on interfacing the

Mx pins to 1.8 V, 3.3 V, or 1.5 V CMOS logic.

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