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Data Sheet

AD9531

PLL2 REGISTERS

PLL2 General Registers—Register 0x0200 Register 0x0201

Table 62. PLL2 General Register Details

Address

Bits

Bit Name

Description

0x0200

[D7:D6]

Unused

Unused.

Reserved

Reserved.

XTAL amplifier

0: configures REF_2P/REF_2N as a differential clock input pair.

1: configures REF_2P/REF_2N as a crystal resonator input. REF_2P/REF_2N is the amplifier input/

output, respectively.

Reserved

Reserved.

Manual sync

Write Logic 1 to arm the distribution synchronization circuit, then write Logic 0 to cause the distribution

channel dividers to synchronize (synchronization occurs on the falling edge of this bit).

Manual calibrate

Logic 1 causes the VCO calibration sequence to execute for PLL2. For robustness, write to this bit

as three operations: Logic 0, Logic 1, then Logic 0.

Power-down

Logic 1 causes a full power-down of PLL2.

0x0201

[D7:D4]

Unused

Unused.

Manual charge

pump current

0: automatic charge pump current control (recommended).

1: enable manual charge pump current control via Register 0x0201, Bits[D2:D0].

[D2:D0]

Charge pump

current [2:0]

Charge pump current control bits. These bits are ineffective when Register 0x0201, Bit D3 = 0.

000: 125 μA.

001: 250 μA.

010: 375 μA.

011: 500 μA.

100: 625 μA.

101: 750 μA.

110: 875 μA.

111: 1000 μA.

PLL2 Frequency Translation Registers—Register 0x0202 to Register 0x0204

Table 63. PLL2 Frequency Translation Register Details

Address

Bits

Bit Name

Description

0x0202

[D7:D4]

Unused

Unused.

[D3:D0]

R2 [3:0]

R2 divider Bit D3 (MSB) to Bit D0. The value of R2 [3:0] results in the following behavior:

0: divides the input frequency by 16.

1 to 15: divides the input frequency by this value.

0x0203

[D7:D0]

N2 [7:0]

N2 Bit D7 (MSB) to Bit D0 (LSB). The value of N2 [7:0] results in the following behavior:

0 to 19: not applicable.

20 to 255: divides by this value.

0x0204

[D7:D4]

Unused

Unused.

[D3:D0]

M2 [3:0]

M2 Bit D3 (MSB) to Bit D0. The value of the M2 [3:0] bits results in the following behavior:

0 to 2: disabled.

3 to 11: divides by this value.

12 to 14: disable.

15: M2 divider reset state. If the user intends to change the M2 divider without performing a

subsequent PLL2 VCO calibration, then program this value (followed by an input/output

update) before programming the a new M2 divider value (followed by an input/output

update). An input/output update is writing Register 0x0005, Bit D0 = 1. The procedure given

here is unnecessary if the user performs a PLL2 VCO calibration after changing the value of M2.

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