AD9531 datasheet(16/88 Pages) AD

номер детали	AD9531

подробное описание детали	3-Channel Clock Generator, 24 Outputs

PDF	88 Pages

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производитель	AD [Analog Devices]

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AD9531

Data Sheet

PLL2 Jitter Generation

The jitter integration bandwidth is from 12 kHz to 20 MHz.

Table 24.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

JITTER GENERATION

fR = 25 MHz, fOUT = 156.25 MHz

0.566

ps rms

fR = 50 MHz, fOUT = 156.25 MHz

0.337

ps rms

PLL2 Spurious Performance

Entries in Table 25 indicate the worst spur measured between dc and 1 GHz on any PLL2 output for the given conditions.

Table 25.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SPURIOUS PERFORMANCE

ROM Profile 4

PLL1: fR = 122.88 MHz, fLOOP = 300 kHz; PLL2: fR = 50 MHz

OUT2_0 to OUT2_4

−61

dBc

OUT2_5 to OUT2_7

−69

dBc

OUT2_8 to OUT2_11

−78

dBc

ROM Profile 5

PLL1: fR = 10 MHz, fVCXO = 122.88 MHz, fLOOP = 100 Hz; PLL2: fR =

50 MHz; PLL3: fR = 10 MHz, CLOAD = 10 pF on OUT3_1P

OUT2_0

−76

dBc

OUT2_1

−65

dBc

OUT2_2 to OUT2_3

−69

dBc

OUT2_4 to OUT2_11

−79

dBc

PLL2 Start-Up Time

Table 26.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

START-UP TIME

The time from the application of power (90% of

nominal) to the first output clock edge (PLL2 is

locked and outputs are synchronized)

fR = 25 MHz, fOUT = 156.25 MHz, fPFD = 25 MHz

Rev. 0 | Page 16 of 88

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