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XIO2001IPNP датащи(PDF) 111 Page - Texas Instruments

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номер детали XIO2001IPNP
подробное описание детали  PCI Express to PCI Bus Translation Bridge
PDF  141 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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XIO2001IPNP датащи(HTML) 111 Page - Texas Instruments

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111
XIO2001
www.ti.com
SCPS212I – MAY 2009 – REVISED JANUARY 2016
Product Folder Links: XIO2001
Submit Documentation Feedback
Copyright © 2009–2016, Texas Instruments Incorporated
Table 82. Pre-Fetch Agent Request Limits Register Description (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:6
PFA_CPL_CACHE_
MODE
RW
Completion cache mode. Determines the rules for completing the caching process.
00 = No caching.
Pre-fetching is disabled.
All remaining read completion data will be discarded after any of the
data has been returned to the PCI master.
01 = Light caching.
Pre-fetching is enabled.
All remaining read completion data will be discarded after data has
been returned to the PCI master and the PCI master terminated the
transfer.
All remaining read completion data will be cached after data has
been returned to the PCI master and the bridge has terminated the
transfer with RETRY.
10 = Full caching.
Pre-fetching is enabled.
All remaining read completion data will be cached after data has
been returned to the PCI master and the PCI master terminated the
transfer.
All remaining read completion data will be cached after data has
been returned to the PCI master and the bridge has terminated the
transfer with RETRY.
11 = Reserved.
5:4
RSVD
R
Reserved. Returns 00b when read.
3:0
PFA_REQ_LENGT
H_LIMIT
RW
Request Length Limit. Determines the number of bytes in the thread that the pre-fetch
agent will read for that thread.
0000 = 64 bytes
0001 = 128 bytes
0010 = 256 bytes
0011 = 512 bytes
0100 = 1 Kbytes
0101 = 2 Kbytes
0110 = 4 Kbytes
0111 = 8 Kbytes
1000:1111 = Reserved



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