XIO2001IPNP datasheet(61/141 Pages) TI1

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XIO2001

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SCPS212I – MAY 2009 – REVISED JANUARY 2016

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8.4.39 Power Management Bridge Support Extension Register

This read-only register indicates to host software what the state of the secondary bus will be when the bridge is

placed in D3. See Table 30 for a complete description of the register contents.

PCI register offset:

4Eh

Read-only

Default value:

40h

BIT NUMBER

RESET STATE

Table 30. PM Bridge Support Extension Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

BPCC

Bus power/clock control enable. This bit indicates to the host software if the bus secondary

clocks are stopped when the bridge is placed in D3. The state of the BPCC bit is

controlled by bit 11 (BPCC_E) in the general control register (offset D4h, see General

Control Register).

0 =

1 =

The secondary bus clocks are not stopped in D3

The secondary bus clocks are stopped in D3

BSTATE

B2/B3 support. This bit is read-only 1b indicating that the bus state in D3 is B2.

5:0

RSVD

Reserved. Returns 00 0000b when read.

8.4.40 Power Management Data Register

The read-only register is not applicable to the bridge and returns 00h when read.

PCI register offset:

4Fh

Read-only

Default value:

00h

BIT NUMBER

RESET STATE

8.4.41 MSI Capability ID Register

This read-only register identifies the linked list item as the register for message signaled interrupts capabilities.

The register returns 05h when read.

PCI register offset:

50h

Read-only

Default value:

05h

BIT NUMBER

RESET STATE

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