XIO2001IPNP datasheet(47/141 Pages) TI1

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XIO2001

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SCPS212I – MAY 2009 – REVISED JANUARY 2016

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8.4.6 Class Code and Revision ID Register

This read-only register categorizes the base class, subclass, and programming interface of the bridge. The base

class is 06h, identifying the device as a bridge. The subclass is 04h, identifying the function as a PCI-to-PCI

bridge, and the programming interface is 00h. Furthermore, the TI device revision is indicated in the lower byte

(03h). See Table 14 for a complete description of the register contents.

PCI register offset:

08h

Read-only

Default value:

0604 0000

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 14. Class Code and Revision ID Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:24

BASECLASS

Base class. This field returns 06h when read, which classifies the function as a bridge device.

23:16

SUBCLASS

Subclass. This field returns 04h when read, which classifies the function as a PCI-to-PCI bridge.

15:8

PGMIF

Programming interface. This field returns 00h when read.

7:0

CHIPREV

Silicon revision. This field returns the silicon revision of the function.

8.4.7 Cache Line Size Register

This register is used to determine when a downstream write is memory write (MW) or memory write invalidate

(MWI).

A posted write TLP will normally be sent as a MW on the PCI bus. It will be sent as a MWI when the following

conditions are met:

•

Cacheline size register has a value that is a power of two (1, 2, 4, 8, 16, 32, 64, or 128)

•

The write starts on a cacheline boundary

•

The write is one or more cachelines in length

•

First and last bytes have all lanes enabled

•

Memory write invalidates are enabled

PCI register offset:

0Ch

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

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