XIO2001IPNP datasheet(77/141 Pages) TI1

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XIO2001

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SCPS212I – MAY 2009 – REVISED JANUARY 2016

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8.4.66 General Control Register

This read/write register controls various functions of the bridge. See Table 49 for a complete description of the

PCI register offset:

D4h

Read-only, Read/Write

Default value:

8600 025Fh

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Table 49. General Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:30(1)

CFG_RETRY_CN

Configuration retry counter. Configures the amount of time that a configuration request must be

retried on the secondary PCI bus before it may be completed with configuration retry status on

the PCI Express side.

00 =

01 =

10 =

11 =

μs

1 ms

25 ms (default)

50 ms

29:28(1)

ASPM_CTRL_DE

F_OVRD

Active State Power Management Control Default Override. These bits are used to determine the

power up default for bits 1:0 of the Link Control Register in the PCI Express Capability Structure.

00 =

01 =

10 =

11 =

Power on default indicates that the active state power management is disable (00b)

(default)

Power on default indicates that the active state power management is enabled for L0s

(01b)

Power on default indicates that the active state power management is enabled for L1s

(10b)

Power on default indicates that the active state power management is enabled for L0s

and L1s (11b)

27(1)

LOW_POWER_E

Low-power enable. When this bit is set, the half-amplitude, no pre-emphasis mode for the PCI

Express TX drivers is enabled. The default for this bit is 0b.

26(1)

PCI_PM_VERSIO

N_CTRL

PCI power management version control. This bit controls the value reported in bits 2:0

(PM_VERSION) in the power management capabilities register (offset 4Ah, see Power

Management Capabilities Register). It also controls the value of bit 3 (NO_SOFT_RESET) in the

power management control/status register (offset 4Ch, see Power Management Control/Status

0 = Version fields reports 010b and NO_SOFT_RESET reports 0b for Power

Management 1.1 compliance

1 = Version fields reports 011b and NO_SOFT_RESET reports 1b for Power

Management 1.2 compliance (default)

25(1)

RSVD

Reserved. Bit 25 defaults to 0b. If this register is programmed via EEPROM or another

mechanism, then the value written into this field must be 0b.

RSVD

Reserved. Returns 0b when read.

23(1)

CPM_EN_DEF_O

VRD

Clock power management enable default override. This bit determines the power-up default for

bits 1:0 (CPM_EN) of the link control register (offset 80h, see Link Control Register) in the PCI

Express Capability structure.

0 = Power-on default indicates that clock power management is disabled (00b) (default)

1 = Power-on default indicates that clock power management is enabled for L0s and L1

(11b)

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