XIO2001IPNP datasheet(29/141 Pages) TI1

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XIO2001

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SCPS212I – MAY 2009 – REVISED JANUARY 2016

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A 14,532-

Ω resistor is a custom value. To eliminate the need for a custom resistor, two series resistors are

recommended: a 14,300-

Ω , 1% resistor and a 232- Ω , 1% resistor. Trace lengths must be kept short to

minimize noise coupling into the reference resistor terminals.

8.3.2.3 Reference Clock

The XIO2001 requires an external reference clock for the PCI-Express interface. The section provide information

concerning the requirements for this reference clock. The XIO2001 is designed to meet all stated specifications

when the reference clock input is within all PCI Express operating parameters. This includes both standard clock

oscillator sources or spread spectrum clock oscillator sources.

The XIO2001 supports two options for the PCI Express reference clock: a 100-MHz common differential

reference clock or a 125-MHz asynchronous single-ended reference clock. Both implementations are described

below.

The first option is a system-wide, 100-MHz differential reference clock. A single clock source with multiple

differential clock outputs is connected to all PCI Express devices in the system. The differential connection

between the clock source and each PCI Express device is point-topoint. This system implementation is referred

to as a common clock design.

The XIO2001 is optimized for this type of system clock design. The REFCLK+ and REFCLK– pins provide

differential reference clock inputs to the XIO2001. The circuit board routing rules associated with the 100-MHz

differential reference clock are the same as the 2.5-Gb/s TX and RX link routing rules itemized in 2.5-Gb/s

Transmit and Receive Links. The only difference is that the differential reference clock does not require series

capacitors. The requirement is a DC connection from the clock driver output to the XIO2001 receiver input.

Terminating the differential clock signal is circuit board design specific. But, the XIO2001 design has no internal

50-

Ω -to-ground termination resistors. Both REFCLK inputs, at approximately 20 k Ω to ground, are high-

impedance inputs.

The second option is a 125-MHz asynchronous single-ended reference clock. For this case, the devices at each

end of the PCI Express link have different clock sources. The XIO2001 has a 125-MHz single-ended reference

clock option for asynchronous clocking designs. When the REFCLK125_SEL input terminal is tied to VDD_33, this

clocking mode is enabled.

The single-ended reference clock is attached to the REFCLK+ terminal. The REFCLK+ input, at approximately

20 k

Ω , is a high-impedance input. Any clock termination design must account for a high- impedance input. The

REFCLK– pin is attached to a 0.1-

μ F capacitor. The capacitor’s second pin is connected to VSSA.

8.3.2.4 Reset

The XIO2001 PCI Express reset (PERST) terminal connects to the upstream PCI Express device’s PERST

output. The PERST input cell has hysteresis and is operational during both the main power state and VAUX power

state. No external components are required.

Please reference the section to fully understand the PERST electrical requirements and timing requirements

associated with power-up and power-down sequencing. Also, the data manual identifies all configuration and

memory-mapped register bits that are reset by PERST.

8.3.2.5 Beacon

The bridge supports the PCI Express in-band beacon feature. Beacon is driven on the upstream PCI Express link

by the bridge to request the reapplication of main power when in the L2 link state. To enable the beacon feature,

bit 10 (BEACON_ENABLE) in the general control register at offset D4h is asserted. See General Control

If the bridge is in the L2 link state and beacon is enabled, when a secondary PCI bus device asserts PME, then

the bridge outputs the beacon signal on the upstream PCI Express link. The beacon signal frequency is

approximately 500 kHz ± 50% with a differential peak-to-peak amplitude of 500 mV and no de-emphasis. Once

the beacon is activated, the bridge continues to send the beacon signal until main power is restored as indicated

by PERST going inactive. At this time, the beacon signal is deactivated.

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