MEC1322 datasheet(155/456 Pages) MICROCHIP

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 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 155

MEC1322

11.15 Emulated 8042 Interface EC-Only Registers

The registers listed in the EC-Only Register Summary table are for a single instance of the Emulated 8042 Interface.

The addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in

the EC-Only Register Base Address Table.

The Base Address indicates where the first register can be accessed in a particular address space for a block instance.

1IBF

Input Buffer Full. This bit is set to “1” whenever the Host writes data

or a command into the HOST_EC Data / CMD Registerr. When this

bit is set, the EC's 8042EM_IBF interrupt is asserted, if enabled.

When the EC reads the HOST_EC Data/CMD Register, this bit is

automatically reset and the interrupt is cleared.

Note:

This bit is not reset when PWRGD is asserted or when

the LPC interface powers down. To clear this bit, firm-

ware must read the EC Data Register in the EC-Only

address space.

R0h

VCC1_R

ESET

0OBF

Output Buffer Full. This bit is set when the EC writes a byte of Data

or AUX Data into the EC_HOST Data / AUX Data Register. When

the Host reads the HOST_EC Data / CMD Register, this bit is auto-

matically cleared by hardware and a 8042EM_OBF interrupt is gen-

erated.

Note:

This bit is not reset when PWRGD is asserted or when

the LPC interface powers down. To clear this bit, firm-

ware must read the HOST_EC Data / CMD Register in

the Runtime address space.

R0h

VCC1_R

ESET

TABLE 11-13: EC-ONLY REGISTER BASE ADDRESS TABLE

Block Instance

Instance Number

Host

Address Space

Base Address

Emulated 8042

Interface

32-bit address

space

400F_0410h

TABLE 11-14: EC-ONLY REGISTER SUMMARY

Offset

HOST2EC Data Register

EC Data Register

EC Keyboard Status Register

Keyboard Control Register

EC AUX Data Register

14h

PCOBF Register

Offset

04h

Bits

Description

Type

Default

Reset

Event

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