MEC1322 datasheet(159/456 Pages) MICROCHIP

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 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 159

MEC1322

11.16 Legacy Port92/GATEA20 Configuration Registers

The registers listed in the Configuration Register Summary table are for a single instance of the Legacy

Port92/GATEA20 logic. The addresses of each register listed in this table are defined as a relative offset to the host

“Base Address” defined in the Configuration Register Base Address Table.

Each Configuration register access through the Host Access Port is via its LDN and its Host Access Port Index. EC

access is a relative offset to the EC Base Address.

11.16.1

PORT 92 ENABLE REGISTER

11.17 Legacy Port92/GATEA20 Runtime Registers

The registers listed in the Runtime Register Summary table are for a single instance of the Legacy Port92/GATEA20

logic. The addresses of each register listed in this table are defined as a relative offset to the host “Base Address”

defined in the Runtime Register Base Address Table.

The Base Address indicates where the first register can be accessed in a particular address space for a block instance.

TABLE 11-15: CONFIGURATION BASE ADDRESS TABLE

Block Instance

Instance

Number

Logical

Device

Number

Host

Address Space

Base Address

Port92-Legacy

LPC

Configuration Port

INDEX = 00h

32-bit internal

address space

400F_1800h

TABLE 11-16: CONFIGURATION REGISTER SUMMARY

Offset

30h

Port 92 Enable Register

Offset

30h

Bits

Description

Type

Default

Reset

Event

7:1 Reserved

0 P92_EN

When this bit is ‘1’, the Port92h Register is enabled. When this bit is

‘0’, the Port92h Register is disabled, and Host writes to LPC

address 92h are ignored.

R/W

PWRGD

and

VCC1_R

ESET

TABLE 11-17: RUNTIME REGISTER BASE ADDRESS TABLE

Block Instance

Instance Number

Host

Address Space

Base Address

Port92-Legacy

LPC

I/O

0092h

32-bit address

space

400F_1800h

TABLE 11-18: RUNTIME REGISTER SUMMARY

Offset

Port 92 Register

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