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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MEC1322 датащи(PDF) 123 Page - Microchip Technology |
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MEC1322 датащи(HTML) 123 Page - Microchip Technology |
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123 / 456 page  2014 - 2015 Microchip Technology Inc. DS00001719D-page 123 MEC1322 9.9.10 INTERRUPT SOURCE MSB REGISTER 9.9.11 INTERRUPT MASK LSB REGISTER 9.9.12 INTERRUPT MASK MSB REGISTER 0EC_WR EC Mailbox Write. This bit is set when the EC-to-HOST Mailbox Register has been written by the EC at offset 01h of the EC-Only registers. Note: there is no corresponding mask bit in the Interrupt Mask LSB Register R0h VCC1_R ESET Offset 09h Bits Description Type Default Reset Event 7:0 EC_SWI_MSB EC Software Interrupt Most Significant Bits. These bits are software interrupt bits that may be set by the EC to notify the host of an event. The meaning of these bits is dependent on the firmware implemen- tation. Each bit in this field is cleared when written with a ‘1b’. The ability to clear the bit can be disabled by the EC. if the corresponding bit in the Host Clear Enable Register is set to ‘0b’. This may be used by firm- ware for events that cannot be cleared while the event is still active. R/WC 0h VCC1_R ESET Offset 0Ah Bits Description Type Default Reset Event 7:1 EC_SWI_EN_LSB EC Software Interrupt Enable Least Significant Bits. Each bit that is set to ‘1b’ in this field enables the generation of a Host Event inter- rupt by the corresponding bit in the EC_SWI field in the Interrupt Source LSB Register. R/W 0h VCC1_R ESET 0 MCHP Reserved R/W 0h VCC1_R ESET Offset 0Bh Bits Description Type Default Reset Event 7:0 EC_SWI_EN_MSB EC Software Interrupt Enable Most Significant Bits. Each bit that is set to ‘1b’ in this field enables the generation of a Host Event inter- rupt by the corresponding bit in the EC_SWI field in the Interrupt Source MSB Register. R/W 0h VCC1_R ESET Offset 08h Bits Description Type Default Reset Event |
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