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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MEC1322 датащи(PDF) 127 Page - Microchip Technology |
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MEC1322 датащи(HTML) 127 Page - Microchip Technology |
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127 / 456 page  2014 - 2015 Microchip Technology Inc. DS00001719D-page 127 MEC1322 9.10.8 MEMORY WRITE LIMIT 1 REGISTER 9.10.9 INTERRUPT SET REGISTER 9.10.10 HOST CLEAR ENABLE REGISTER Offset 12h Bits Description Type Default Reset Event 15 Reserved R - - 14:2 MEMORY_WRITE_LIMIT_1 Whenever a write of any byte in EC DATA Register is attempted and bit 15 of EC_Address is 1, the field EC_Address[14:2] in the EC_Ad- dress Register is compared to this field. As long as EC_Ad- dress[14:2] is less than Memory_Write_Limit_1[14:2] the addressed bytes in the EC DATA Register will be written into the internal 24-bit address space. If EC_Address[14:2] is greater than or equal to the Memory_Write_Limit_1[14:2] no writes will take place. R/W 0h VCC1_R ESET 1:0 Reserved R - - Offset 14h Bits Description Type Default Reset Event 15:1 EC_SWI_SET EC Software Interrupt Set. This register provides the EC with a means of updating the Interrupt Source Registers. Writing a bit in this field with a ‘1b’ sets the corresponding bit in the Interrupt Source Register to ‘1b’. Writing a bit in this field with a ‘0b’ has no effect. Reading this field returns the current contents of the Interrupt Source Register. R/WS 0h VCC1_R ESET 0 Reserved R - - Offset 16h Bits Description Type Default Reset Event 15:1 HOST_CLEAR_ENABLE When a bit in this field is ‘0b’, the corresponding bit in the Interrupt Source Register cannot be cleared by writes to the Interrupt Source Register. When a bit in this field is ‘1b’, the corresponding bit in the Interrupt Source Register can be cleared when that register bit is written with a ‘1b’. These bits allow the EC to control whether the status bits in the Inter- rupt Source Register are based on an edge or level event. R/W 0h VCC1_R ESET 0 Reserved R - - |
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