MEC1322 datasheet(108/456 Pages) MICROCHIP

108 / 456 page

MEC1322

DS00001719D-page 108

 2014 - 2015 Microchip Technology Inc.

7.6

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

7.6.1

POWER DOMAINS

7.6.2

CLOCK INPUTS

7.6.2.1

Basic Clocking

The basic clocking comes from a free-running Clock signal provided from the chip level.

7.6.2.2

System Tick Clocking

The System Tick clocking is controlled by a signal from chip-level logic. It is the 48 MHz Ring Oscillator divided by the

following:

-((Processor Clock Divide Value)x2)+1.

7.6.2.3

Debug JTAG Clocking

The Debug JTAG clocking comes from chip-level logic, which may multiplex or gate this clock. See Section 7.9.3,

"Debugger Access Support," on page 111.

7.6.2.4

Trace Clocking

The Clock for the Trace interface is identical to the 48 MHz Ring Oscillator input.

7.6.3

RESETS

The reset interface from the chip level is given below.

7.7

Interrupts

The ARM M4F Based Embedded Controller is equipped with an Interrupt Interface to respond to interrupts. These inputs

go to the IP’s NVIC block after a small amount of hardware processing to ensure their detection at varying clock rates.

See FIGURE 7-1: ARM M4F Based Embedded Controller I/O Block Diagram on page 107.

As shown in Figure 7-1, an Interrupt Aggregator block may exist at the chip level, to allow multiple related interrupts to

be grouped onto the same NVIC input, and so allowing them to be serviced using the same vector. This may allow the

same interrupt handler to be invoked for a group of related interrupt inputs. It may also be used to expand the total num-

ber of interrupt inputs that can be serviced.

Connections to the chip-level system are given in Table 15-3, “Interrupt Event Aggregator Routing Summary,” on

page 195.

The NMI (Non-Maskable Interrupt) connection is tied off and not used.

TABLE 7-1:

POWER SOURCES

Name

Description

VCC1

The ARM M4F Based Embedded Controller is powered by VCC1.

TABLE 7-2:

CLOCK INPUTS

Name

Description

48 MHz Ring Oscillator

The EC clock derived from the 48 MHz Ring Oscillator is the clock

source to the ARM M4F Based Embedded Controller. Division of the

clock rate is allowed, according to the Processor Clock Enable.

Note:

The EC clock is controlled from the chip-level Power, Clocks,

and Reset (PCR) circuitry. See Section 3.9.8, "Processor

Clock Control Register (PROC_CLK_CNTRL)," on page 61.

TABLE 7-3:

RESET SIGNALS

Name

Description

EC_PROC_ RESET

The ARM M4F Based Embedded Controller is reset by EC_PROC_

RESET.

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