MEC1322 datasheet(105/456 Pages) MICROCHIP

105 / 456 page

 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 105

MEC1322

• Interface standard for Trace data to the TPIU from ETM and/or ITM blocks, Defined in AMBA 3. See ARM Limited:

AMBA® 3 ATB Protocol Specification, IHI0032A, 19 June 2006.

•AMBA

• The collective term for bus standards originated by ARM Limited.

• AMBA 3 defines the IP’s AHB-Lite and ATB bus interfaces.

• AMBA 2 (AMBA Rev. 2.0) defines the EC’s AHB bus interface.

•AHB

• Advanced High-Performance Bus, a system-level on-chip AMBA 2 bus standard. See ARM Limited: AMBA®

Specification (Rev 2.0), IHI0011A, 13 May 1999.

•AHB-Lite

• A Single-Master subset of the AHB bus standard: defined in the AMBA 3 bus standard. See ARM Limited:

AMBA® 3 AHB-Lite Protocol Specification, IHI0033A, 6 June 2006.

• PPB

• Private Peripheral Bus: A specific APB bus with local connectivity within the EC.

• APB

• Advanced Peripheral Bus, a limited 32-bit-only bus defined in AMBA 2 for I/O register accesses. This term is rele-

vant only to describe the PPB bus internal to the EC core. See ARM Limited: AMBA® Specification (Rev 2.0),

IHI0011A, 13 May 1999.

•MPU

• Memory Protection Unit. This is an optional subblock that is not currently included.

•HTM

• AHB Trace Macrocell. This is an optional subblock that is not currently included.

•WIC

• Wake-Up Interrupt Controller. This is an optional subblock that is not currently included.

7.3.2

MICROCHIP TERMS AND ACRONYMS

• PMU

• This Processor Memory Unit is a module that may be present at the chip level containing any memory resources

that are closely-coupled to the MEC1322 EC. It manages accesses from both the EC processor and chip-level bus

masters.

• Interrupt Aggregator

• This is a module that may be present at the chip level, which can combine multiple interrupt sources onto single

interrupt inputs at the EC, causing them to share a vector.

7.4

ARM M4F IP Interfaces

This section defines only the interfaces to the ARM IP itself. For the interfaces of the entire block, see Section 7.5, "Block

External Interfaces," on page 107.

The MEC1322 IP has the following major external interfaces, as shown in FIGURE 7-1: ARM M4F Based Embedded

Controller I/O Block Diagram on page 107:

• ICode AHB-Lite Interface

• DCode AHB-Lite Interface

• System AHB-Lite Interface

• Debug (JTAG) Interface

• Trace Port Interface

• Interrupt Interface

The EC operates on the model of a single 32-bit addressing space of byte addresses (4Gbytes, Von Neumann archi-

tecture) with Little-Endian byte ordering. On the basis of an internal decoder (part of the Bus Matrix shown in Figure 7-

1), it routes Read/Write/Fetch accesses to one of three external interfaces, or in some cases internally (shown as the

PPB interface).

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