MEC1322 datasheet(111/456 Pages) MICROCHIP

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DS00001719D-page 111

MEC1322

7.9.2

INSTRUCTION PIPELINING

There are no special considerations except as defined by ARM documentation.

7.9.3

DEBUGGER ACCESS SUPPORT

An external Debugger accesses the chip through a JTAG standard interface. The debugger itself, however, is not an

ARM product, and its capabilities will depend on the third-party product selected for code development and debug.

As shown in FIGURE 7-1: ARM M4F Based Embedded Controller I/O Block Diagram on page 107, there may be other

resources at the chip level that share the JTAG port pins; for example chip-level Boundary Scan. See Section 1.4.4,

"JTAG Interface," on page 15 for configuring the JTAG pins at the chip level for Debug purposes.

7.9.3.1

Debug and Access Ports (SWJ-DP and AHB-AP Subblocks)

These two subblocks work together to provide access to the chip for the Debugger using the Debug JTAG connection,

as described in Chapter 4 of the ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 Feb-

ruary 2006.

7.9.4

BREAKPOINT, WATCHPOINT AND TRACE SUPPORT

See ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 February 2006 and also ARM Lim-

ited: ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement, DSA09-PRDC-008772, 17 August

2009. A summary of functionality follows.

Breakpoint and Watchpoint facilities can be programmed to do one of the following:

• Halt the processor. This means that the external Debugger will detect the event by periodically polling the state of

the EC.

• Transfer control to an internal Debug Monitor firmware routine, by triggering the Debug Monitor exception (see

Table 7-4, “Exception and Interrupt Vector Table Layout,” on page 109).

7.9.4.1

Instrumentation Support (ITM Subblock)

The Instrumentation Trace Macrocell (ITM) is for profiling software. This uses non-blocking register accesses, with a

fixed low-intrusion overhead, and can be added to a Real-Time Operating System (RTOS), application, or exception

handler. If necessary, product code can retain the register access instructions, avoiding probe effects.

7.9.4.2

HW Breakpoints and ROM Patching (FPB Subblock)

The Flash Patch and Breakpoint (FPB) block. This block can remap sections of ROM, typically Flash memory, to regions

of RAM, and can set breakpoints on code in ROM. This block can be used for debug, and to provide a code or data

patch to an application that requires field updates to a product in ROM.

7.9.4.3

Data Watchpoints and Trace (DWT Subblock)

The Debug Watchpoint and Trace (DWT) block provides watchpoint support, program counter sampling for performance

monitoring, and embedded trace trigger control.

7.9.4.4

Trace Interface (ETM and TPIU)

The Embedded Trace Macrocell (ETM) provides instruction tracing capability. For details of functionality and usage, see

also ARM Limited: Embedded Trace Macrocell™ (ETMv1.0 to ETMv3.5) Architecture Specification, IHI0014Q, 23 Sep-

tember 2011 and ARM Limited: CoreSight™ ETM™-M4 Technical Reference Manual, DDI0440C, 29 June 2010.

The Trace Port Interface Unit (TPIU) provides the external interface for the ITM, DWT and ETM.

See Section 1.4.16, "Trace Debug Interface," on page 19 for configuring the Trace pins at the chip level for Trace output.

7.10

ARM Configuration

In order to function correctly, it is necessary to set the ARM Auxiliary Control Register (ACTLR), located at address 0xE-

000E008, to 0x02. This sets bit[1], DISDEFWBUF, to 1. This must be done as soon as possible after Power On Reset,

or register corruption may occur.

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