MEC1322 datasheet(223/456 Pages) MICROCHIP

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 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 223

MEC1322

17.5.1

POWER DOMAINS

17.5.2

CLOCK INPUTS

17.5.3

RESETS

17.6

Interrupts

17.7

Low Power Modes

The Basic Timer may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry. This block

is only be permitted to enter low power modes when the block is not active.

The sleep state of this timer is as follows:

• Asleep while the block is not Enabled

• Asleep while the block is not running (start inactive).

• Asleep while the block is halted (even if running).

The block is active while start is active.

TABLE 17-1:

POWER SOURCES

Name

Description

VCC1

The timer control logic and registers are all implemented on this single

power domain.

TABLE 17-2:

CLOCK INPUTS

Name

Description

48 MHz Ring Oscillator

This is the clock source to the timer logic. The Pre-scaler may be used

to adjust the minimum resolution per bit of the counter.

TABLE 17-3:

RESET SIGNALS

Name

Description

VCC1_RESET

This reset signal, which is an input to this block, resets all the logic and

registers to their initial default state.

Soft Reset

This reset signal, which is created by this block, resets all the logic and

registers to their initial default state. This reset is generated by the block

when the SOFT_RESET bit is set in the Timer Control Register register.

Timer_Reset

This reset signal, which is created by this block, is asserted when either

the VCC1_RESET or the Soft Reset signal is asserted. The VCC1_RE-

SET and Soft Reset signals are OR’d together to create this signal.

TABLE 17-4:

EC INTERRUPTS

Source

Description

TIMER_16_x

This interrupt event fires when a 16-bit timer x reaches its limit. This

event is sourced by the EVENT_INTERRUPT status bit if enabled.

TIMER_32_x

This interrupt event fires when a 32-bit timer x reaches its limit. This

event is sourced by the tEVENT_INTERRUPT status bit if enabled.

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