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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MEC1322 датащи(PDF) 220 Page - Microchip Technology |
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MEC1322 датащи(HTML) 220 Page - Microchip Technology |
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220 / 456 page  MEC1322 DS00001719D-page 220 2014 - 2015 Microchip Technology Inc. 16.7.1.4 WDT Interval The WDT Interval is the time it takes for the WDT to decrements from the WDT Load Register value to 0000h. The WDT Count Register value takes 33/32KHz_Clk seconds (ex. 33/32.768 KHz = 1.007ms) to decrement by 1 count. 16.8 EC-Only Registers The registers listed in the EC-Only Register Summary table are for a single instance of the Watchdog Timer (WDT). The addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the EC-Only Register Base Address Table. The Base Address indicates where the first register can be accessed in a particular address space for a block instance. 16.8.1 WDT LOAD REGISTER 16.8.2 WDT CONTROL REGISTER TABLE 16-5: EC-ONLY REGISTER BASE ADDRESS TABLE Block Instance Instance Number Host Address Space Base Address WDT 0 EC 32-bit internal address space 4000_0400h TABLE 16-6: EC-ONLY REGISTER SUMMARY Offset Register Name (Mnemonic) 00h WDT Load Register 04h WDT Control Register 08h WDT Kick Register 0Ch WDT Count Register Offset 00h Bits Description Type Default Reset Event 15:0 WDT Load Writing this field reloads the Watch Dog Timer counter. R/W Fh VCC1_R ESET Offset 04h Bits Description Type Default Reset Event 7:2 RESERVED R - - 1 WDT Status WDT_RST is set by hardware if the last reset of MEC1322 was caused by an underflow of the WDT. See Section 16.7.1.3, "WDT Reload Mechanism," on page 219 for more information. This bit must be cleared by the EC firmware writing a ‘1’ to this bit. Writing a ‘0’ to this bit has no effect. R/WC 0b VCC1_R ESET |
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