MEC1322 datasheet(226/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 226

 2014 - 2015 Microchip Technology Inc.

17.9.4

TIMER INT ENABLE REGISTER

17.9.5

TIMER CONTROL REGISTER

Offset

0Ch

Bits

Description

Type

Default

Reset

Event

31:0 Reserved

0 EVENT_INTERRUPT_ENABLE

This is the interrupt enable for the status EVENT_INTERRUPT bit in

the Timer Status Register

R/W

Tim-

er_Reset

Offset

10h

Bits

Description

Type

Default

Reset

Event

31:16 PRE_SCALE

This is used to divide down the system clock through clock enables

to lower the power consumption of the block and allow slow timers.

Updating this value during operation may result in erroneous clock

enable pulses until the clock divider restarts.

The number of clocks per clock enable pulse is (Value + 1); a setting

of 0 runs at the full clock speed, while a setting of 1 runs at half

speed.

R/W

Tim-

er_Reset

15:8 Reserved

7HALT

This is a halt bit. This will halt the timer as long as it is active. Once

the halt is inactive, the timer will start from where it left off.

1=Timer is halted. It stops counting. The clock divider will also be

reset.

0=Timer runs normally

R/W

Tim-

er_Reset

6RELOAD

This bit reloads the counter without interrupting it operation. This will

not function if the timer has already completed (when the START bit

in this register is ‘0’). This is used to periodically prevent the timer

from firing when an event occurs. Usage while the timer is off may

result in erroneous behavior.

R/W

Tim-

er_Reset

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