MEC1322 datasheet(202/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 202

 2014 - 2015 Microchip Technology Inc.

15.8.3

DISABLING INTERRUPTS

The Block Enable Clear Register and Block Enable Set Register should not be used for disabling and enabling interrupts

for software operations i.e., critical sections. The ARM enable disable mechanisms should be used.

15.9

EC-Only Registers

The configuration registers listed in EC-Only Register Summary table are for a single instance of the EC Interrupt Aggre-

gator. The addresses of each register listed in the summary table are defined as a relative offset to the host “Begin

Address” defined in the EC-Only Register Base Address Table.

Note 15-1

The Begin Address indicates the location of the first register accessable at offset 00h in the Interrupt

Aggregator EC-Only address space.

IRQ27

ILINK1

level 1 (low)

D8h

IRQ28

ILINK1

level 1 (low)

E0h

IRQ29

ILINK1

level 1 (low)

E8h

IRQ30

ILINK1

level 1 (low)

F0h

IRQ31

ILINK1

level 1 (low)

F8h

Note:

IRQ Vector 31 is the highest L1 Priority

TABLE 15-5:

EC-ONLY REGISTER ADDRESS RANGE TABLE

Instance Name

Instance

Number

Host

Address Space

Begin Address

(

Note 15-1)

Interrupt Aggregator

32-bit internal

address space

4000_C000h

TABLE 15-6:

EC-ONLY REGISTER SUMMARY

Offset

00h

GIRQ8 Source Register

04h

GIRQ8 Enable Set Register

08h

GIRQ8 Result Register

0Ch

GIRQ8 Enable Clear Register

14h

GIRQ9 Source Register

18h

GIRQ9 Enable Set Register

1Ch

GIRQ9 Result Register

20h

GIRQ9 Enable Clear Register

28h

GIRQ10 Source Register

2Ch

GIRQ10 Enable Set Register

30h

GIRQ10 Result Register

34h

GIRQ10 Enable Clear Register

3Ch

GIRQ11 Source Register

40h

GIRQ11 Enable Set Register

44h

GIRQ11 Result Register

48h

GIRQ11 Enable Clear Register

TABLE 15-4:

EC INTERRUPT STRUCTURE (CONTINUED)

Vector

Name

Link

Priority

(Default)

Relative

Priority

Byte

Offset

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